Hi Heystek

I notice that you are using Xilinx Output Gateways leading to scopes, I
would guess that there are Input Gateway/s as well. These will be linked to
physical pins, or software interfaces, on the FPGA when compiled. If you
want to access inputs linked to FPGA pins or software interfaces, these are
provided in our toolflow via the yellow blocks. We do not allow users to
instantiate these outside of yellow blocks to prevent Bad Things From
Happening.

Regards
Andrew


On Tue, Aug 11, 2020 at 3:39 PM Heystek Grobler <[email protected]>
wrote:

> Hey James
>
> Below is a snipped:
>
>
>
> On 11 Aug 2020, at 15:24, James Smith <[email protected]> wrote:
>
> Send a screen snip of what you've got, Heystek?
>
> On Tue, Aug 11, 2020 at 1:22 PM Heystek Grobler <[email protected]>
> wrote:
>
>> Hey James and Mugundhan
>>
>> Thank you for your emails.
>>
>> Yes, I have a Shared BRAM block in my design. The BRAM block is from the
>> casper blockset. So I should rather use something else for the design?
>>
>> On 11 Aug 2020, at 15:03, James Smith <[email protected]> wrote:
>>
>> Hello Heystek,
>>
>> Somewhere in your design, you are trying to use a Xilinx block as an
>> input. Replace it with one of the yellow blocks from the Casper tools, and
>> you should be okay. (Usually this will be a software register or a BRAM
>> block.)
>>
>> Regards,
>> James
>>
>>
>> On Tue, Aug 11, 2020 at 12:54 PM Heystek Grobler <
>> [email protected]> wrote:
>>
>>> Good day everyone
>>>
>>> I am compiling a design for Roach2. I can into this error when running
>>> casper_xps:
>>>
>>> "xilinx input gateways cannot be used in a design. Only gpio blocks”
>>>
>>> How can I solve this or am I doing something stupid?
>>>
>>> Thanks for the help
>>>
>>> Heystek
>>>
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