I'm working on a design where the input sources to the Red Pitaya are switched at ~4Hz for calibration purposes. I was implementing functionality to prevent data from one calibration state ending up in the accumulator during the next calibration state, and I started getting some strange behavior from my simulation. A bit of digging turned up this:
https://forums.xilinx.com/t5/AI-Engine-DSP-IP-and-Tools/Xilinx-FFT-Block-In-Out-Sync-problem/td-p/975620 TL;DR: The start frame in/out on the Simulink FFT block do not behave *quite* as advertised, and there is significant discrepancy between simulation and hardware performance. If your design only needs 1 sync pulse and then runs continuously, this bug does not affect it. Looks like this has been patched in Xilinx 2020.1, but then I would lose support for all of the Casper goodies! Guess I'll try to get creative with the vector accumulator triggers. -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/b75d7f6d-69ad-4c36-a10d-ccfff1c1cbefo%40lists.berkeley.edu.
