Hi,Dan Thanks for you reply.
The adc_mkid_4x yellow block for ROACH2 was designed by Madden, Timothy J. From mail list I found that it has some different from the yellow block for ROACH. If you have some results,please inform me Thank you. Cheers! >------------------------------------------------------------------------ ZHANG Laiyu Phone(China) 010-88233078 Cellphone(China) 13681385567 E-mail: [email protected] Address: 19B Yuquan Road,Shijingshan District,Beijing，China Department: Center for Particle Astrophysics Office: Astrophysics Building 205 Institute of High Energy Physics, CAS web: http://www.ihep.cas.cn >------------------------------------------------------------------------ -----原始邮件----- 发件人:"Dan Werthimer" <[email protected]> 发送时间:2020-10-27 02:48:59 (星期二) 收件人: [email protected] 抄送: [email protected], "CASPER Mailing List" <[email protected]>, "Rick Raffanti" <[email protected]> 主题: Re: [casper] MKID ADC-4x problem the clock rate of FPGA hi ZHANG Laiyu, from rick, who designed that ADC board: "The ADC produces full-parallel data at 550 or 400MHz DDR, so the ADC core would normally run at half of this- I don't see any reason to run it slower. I can't remember who did the yellow block; I have code that runs on a mini-roach for testing these. Rick" On Wed, Oct 21, 2020 at 2:21 AM zhang laiyu <[email protected]> wrote: Hi,all I use ROACH2 and MKID ADC-4x board(2*ADS54RF63) to acquire data and send it through 10Gb to computer. I use adc_mkid_4x yellow block in the firmware. Now,I can get data from 10Gb . But I found that the data package have repeated data. When I input the ADC_I with 100KHz sine signal (Vpp is 200mv). I can get the curve,but is not very correct.From the raw data, I fount every 8 data(12bits),exist 4 point was same. datapackage like: d1d2d3d4d1d2d3d4d5d6d7d8d5d6d7d8....It sames that the FPGA's clock is 1/2 of ADC clock. When I modified the firmware,replace the adc yellow block with counters,I can get right data. There are not repeat data. So I suspected that the FPGA's clock is 1/2 of MKID-ADC clock. From MKID ADC boad schematic design，the clock send to FPGA is 1/2 ADC clock. But from the mail list and other papers,I got that the clock rate of FPGA should be 1/4 ADC clock generated by adc_mkid_4x yellow block. Anyone can give me some help or suggestion? Attachment is firmware and one test result curve. Thanks. Cheers! >------------------------------------------------------------------------ ZHANG Laiyu Phone(China) 010-88233078 Cellphone(China) 13681385567 E-mail: [email protected] Address: 19B Yuquan Road,Shijingshan District,Beijing，China Department: Center for Particle Astrophysics Office: Astrophysics Building 205 Institute of High Energy Physics, CAS web: http://www.ihep.cas.cn >------------------------------------------------------------------------ -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/385ac38a.2cdee.1754a768364.Coremail.zhangly%40ihep.ac.cn. -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/75af4cf3.30251.17568bf8890.Coremail.zhangly%40ihep.ac.cn.
