Hello Idir,

Do you have the SLX file? Can you share which version of matlab that you're
using? I can possibly take a look tomorrow.  (Email me directly if you
don't want to share it in a public space.)

Regards,
James


On Mon, Nov 9, 2020 at 5:49 PM Idir Mellal <[email protected]> wrote:

> Hi James,
>
> Thanks for your answer.
>
> I do not use a CASPER. I am using a ZCU102 platform.
> For the frequency, you're right. The initial period was 10ns, but I
> didn't get the expected response. So I started changing the frequency.
>
> Please do not hesitate if you have any other suggestions.
>
> Best regards,
> idir.
>
> On Sun, Nov 8, 2020 at 11:36 PM James Smith <[email protected]> wrote:
>
>> Hello Idir,
>>
>> It's been a while since I've played around with this, but it looks as
>> though you've chosen some fairly strange settings there.
>>
>> We don't usually manipulate the settings in the Xilinx Sysgen block
>> directly - it's usually done through one of the CASPER yellow blocks -
>> depending on what FPGA platform we are using. Are you using the CASPER
>> tools at all? Or SysGen directly?
>>
>> Generally you have to consider one FPGA clock as one "tick" in Simulink.
>> So you'll have to scale your X-axis appropriately for your simulated output.
>>
>> It looks as though you've got a clock period set of 50 million nanosecons
>> - or about 20 Hz if my maths isn't totally wrong? No FPGA that I know of
>> will clock itself that low - I'm not sure how smart Sysgen is, but it might
>> be ignoring the value you've set as out of range and going with some
>> default.
>>
>> Regards,
>> James
>>
>>
>> On Fri, Nov 6, 2020 at 3:00 PM Idir Mellal <[email protected]> wrote:
>>
>>> Hi Fulks,
>>>
>>> I want to implement a complex neuronal model, biological neurons, using
>>> the Xilinx System Generator. I developed a Matlab model and did the
>>> simulations for 2 s to validate it. After that, I realized a hardware
>>> architecture using SysGen.
>>>
>>> The problem I am facing is the results are not correlated in terms of
>>> timing, I don't know the appropriate setting to simulate 2s on the FPGA!
>>> I summarized the model in the attached file.
>>>
>>> Please let me know if you have any solution or suggestion.
>>> I really appreciate your help.
>>>
>>> Best regards,
>>> Idir.
>>>
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