Hi Sebastian

To add to what Dave has suggested.

As you mention, significant time is taken to do the 'Update' before the
actual simulation is run. To prevent having to do this every time a
simulation runs, keep the design open rather than closing and re-opening.
Parameter changes often do not affect all blocks, so even changing
parameters on an already 'Updated' design is quicker than opening it from
scratch.

To go further - parf of the 'Update' includes redrawing parts that need to
be based on design parameters. Even if only one parameter in a subsystem is
changed, a lot of the contents can be redrawn.  It might be worth making
different Simulink models with different parameters rather than changing
the parameters on a single design if the parameter changes trigger
significant redraws.

To add to Dave's 'simulate in hardware' idea - there are what we call
'snapshot' blocks in the Scopes subsection of the CASPER DSP Blockset
Simulink block library that are very useful and have software support in
casperfpga to help in operation, unpacking the data etc. There are also
some useful test vector generator blocks in the Sources subsection.

Regards
Andrew


On Thu, Sep 16, 2021 at 1:34 AM David Harold Edward MacMahon <
[email protected]> wrote:

> Hi, Sebastian,
>
> If you're only changing the inputs (i.e. NOT changing parameters of the
> CASPER blocks), you might want to consider building a test design that
> allows you to provide the inputs via a "Shared BRAM" block and reading the
> output from another "Shared BRAM" block.  Then you could "simulate" in
> hardware (assuming you have hardware...), which will be very much faster.
>
> If you're changing the parameters of the CASPER blocks, then perhaps
> testing with a smaller PFB/FFT would speed things up while you hone in on
> the parameters you want to explore in more depth.  Then you can try a
> smaller set of tests on the larger PFB/FFT.
>
> HTH,
> Dave
>
> On Sep 15, 2021, at 10:57, Sebastian Antonio Jorquera Tapia <
> [email protected]> wrote:
>
> Hi, I am trying to simulate a model with a correlator using two
> pfbs+widebands ffts, and currently my biggest problem is the simulation
> time. For example for ~6000 cycles, the simulation takes up to 15 minutes
> and I would like to repeat it for like 4000 cases.
>
> I am using enabled subsystem with "to workspace" inside of it, to take a
> look to the outputs, that way I just save the valid values which are a
> fraction of the whole simulation time.
> Also if it matters i am running the simulation programmatically using the
> sim function (I have the belief that way is faster, but I havent measure
> it).
>
> I think that the slowest part is when matlab reviews the design (I am not
> fully confident of what matlabs does previous the call to the xilinx
> simulator).
> So I tried to compile the pfb+ffts into a hdl netlist and import it with a
> black box to simulink, but my computers freeze after the xilinx token
> appears :(
>
> There is a way to improve the simulation time??
>
>
>
>
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