Hi Jack,

Thanks for your reply. I will read this document carefully.

Cheers
Wang

Jack Hickish <[email protected]> 于2022年8月31日周三 16:35写道:

> Hi Wang,
>
> If you haven't seen it already, this memo is probably useful --
> https://github.com/casper-astro/publications/blob/master/Memos/files/Black_box_memo.pdf
>
> The PCORE yellow block doesn't contain anything because it doesn't
> actually do anything in FPGA logic. All it does is tells the toolflow to
> include extra source files in your build, which should have been
> pre-generated. The memo above explains how to do this.
>
> Cheers
> Jack
>
> On Wed, 31 Aug 2022 at 09:00, Morag Brown <[email protected]> wrote:
>
>> Hi Wang,
>>
>> I can't answer the first question, and your third is a bit confusing. Can
>> you send a screenshot of the block you mean?
>>
>> As for the shared_bram - this instantiates bram on hardware that is
>> exposed to the axi/wishbone (depending on the hardware) bus. You can write
>> values (*vals*) to this block via casperfpga by packing your data using "*buf
>> = struct.pack('>1024i', *vals)"*, and then write to the bram using* 
>> "fpga.write('memory
>> device name', buf, offset)"*. To read from the bram you would do a 
>> "*struct.unpack('>1024i',
>> fpga.read('memory device name',1024*4,0))"* call - the values 1024, 4
>> and *i* will change depending on the depth of you bram and your data
>> width. Within the design, you need to have a counter on the address line to
>> iterate through the addresses that you are writing to, and if you are
>> planning on writing to the block via casperfpga then you should set *write
>> enable *and *data input* to 0; and if you are planning to write in over
>> the data line, then *write enable* should be set high with the data line
>> tied to wherever your values are coming from. In simulation, you can write
>> an array of values (for simulation only) to the "initial values" text box
>> within the block that opens when you double click. Then to see what the
>> output is doing, you can add a simulink scope block to the bram output.
>>
>> Hope this helps a bit!
>>
>> Morag
>>
>> On Wed, Aug 31, 2022 at 7:48 AM Wang <[email protected]> wrote:
>>
>>> Hello CASPER,
>>>
>>> I am currently looking at David's simulink model of PAPER correlator and
>>> some other people built simulink models.
>>>
>>> I met some questions in the process of looking at it.
>>> I have been exposed to simulink for a short time and it is not clear how
>>> some modules work.
>>>
>>> The first question.Double-click on the PCORE block and prompt me for a
>>> path. I imitate David's input, but no response. Then I check David's PCORE
>>> block inside also nothing, may I ask what is wrong with my operation?
>>>
>>> The second question.I see Share_BRAM blocks used a lot. I want to
>>> understand the details of this block, the official website does not seem to
>>> have Share_BRAM description. Also, I want to see what is happening to
>>> Share_BRAM during simulation. What blocks can I do this with?
>>>
>>> The third question.I see that a yellow block (not the same color as
>>> Casper-libary's block)  does not have a library link. A window appears
>>> after double-click :
>>> Function Block Parameters: block's name
>>> Subsystem (mask)
>>> Parameters
>>> Number of fft channels (same ad fft prompt)(2^?)
>>> Is it a Subsystem block? If yes, how to add the function of double click
>>> setting parameter?
>>>
>>> I really hope you can reply to me, I will be very grateful!
>>>
>>> BW
>>> Wang
>>>
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