Dear Mitch Burnett, Thank you for the prompt response. I have read elsewhere that external software is needed to program the Texas Instruments LMK04828. In particular, the software is run at board startup, and is used to change the input clock source, or modify the LMK's output frequencies, according to application. Downstream of the LMK, the FPGA would use the clocks denoted by "PL RF SYS REFCLK" and "PL SYS REFCLK". This would tentatively be the workflow for having the 4x2 board synched to an external GSPDO. There are programming utilities for PYNQ framework, but I don't know of any analogous software for CASPER. Maybe you know of what could be used for that? On Tuesday, June 6, 2023 at 11:56:18 AM UTC-4 Mitch Burnett wrote:
> Hi Ken, > > There are not any good examples in the CASPER Tutorials yet for how to > configure this, however the capability is there. > > In CASPER tools the signals out of the comparator/ADS7885S/etc. in that > diagram and into the FPGA fabric are accessed via a GPIO yellow block using > the name given to the signal in the platform configuration file. This is > similar for example to how to use LEDs in the toolflow. The platform yellow > block needs to be extended to include these signal names. That process > involves taking the schematic net name and adding it to the platform file > along with the corresponding package pin to the rfsoc. > > In this case you could add the following to the rfsoc4x2.yaml platform > file: > > ``` > irig_adc_sdo: > iostd: LVCMOS18 > loc: AK13 > irig_adc_sclk: > iostd: LVCMOS18 > loc: AH12 > Irig_comp_out: > iostd: LVCMOS18 > loc: AJ13 > irig_trig_out: > iostd: LVCMOS18 > loc: AH13 > ``` > > With this added, and using a GPIO yellow block where the name in the > configuration window for that block is any of `irig_*` names you are > locking target, you should be getting these signals into your fabric design. > > Hope this helps, > > Mitch > > On Jun 5, 2023, at 8:27 PM, Ken Semanov <[email protected]> wrote: > > *board = Zynq UltraScale+ RFSoC4x2board (Gen 3 ZU48DR)* > *.* > > <smlexternal_PPS.png> > The above shows an external PPS driving an ADC that is SPI's into the > XCZU48DR. In what manner would the FPGA fabric access these pins in a > design? Should the PLLs be programmed externally to align with this > input? > > I have not seen any of these names re-occurring in say Xilinx document > pg269, nor in Zynq document ug1085 (the full tech ref manual). How could > these pins be accessed? > > Has anyone had luck in accessing the 1PPS SMA there, say for connecting to > an external GPSDO? Thank you. > > > -- > You received this message because you are subscribed to the Google Groups " > [email protected]" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > To view this discussion on the web visit > https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/969d90a1-5bca-4325-8718-f9b4e53838f9n%40lists.berkeley.edu > > <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/969d90a1-5bca-4325-8718-f9b4e53838f9n%40lists.berkeley.edu?utm_medium=email&utm_source=footer> > . > <smlexternal_PPS.png> > > > -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/606ce9f7-22b3-4aef-8ae5-4c3279dc3dc0n%40lists.berkeley.edu.
