Also potentially confusing for us new users is that the example rfsoc
starts file <
https://github.com/casper-astro/tutorials_devel/blob/main/rfsoc/startsg.local.example>
incorrectly sets JASPER_BACKEND=vivado

Jason


On Fri, Jun 9, 2023 at 7:04 AM Jason Gallicchio <[email protected]> wrote:

> I too was stuck on this for at least a day. I had JASPER_BACKEND=vivado
> from the previous tutorial or from <
> https://casper-toolflow.readthedocs.io/en/latest/src/Configuring-the-Toolflow.html>
> and the rfsoc getting started tutorial doesn't really call attention to
> this change.
>
> Even just a comment in the tutorial would help like :
> export JASPER_BACKEND=vitis  # use vitis rather than vivado to  build both
> .fpg and .dtbo for RFSoC
>
> Jason
>
>
> On Fri, Jun 9, 2023 at 1:14 AM Jonathon Kocz <[email protected]> wrote:
>
>> Hi Cedric and Nhung,
>>
>> A couple of things to check:
>>
>> 1) Have you updated the startsg.local file with the paths for creating
>> the .dtbo files?
>>
>> You'll need to set the JASPER_BACKEND to vitis also (e.g):
>>
>> JASPER_BACKEND=vitisXLNX_DT_REPO_PATH=</path/to>/sandbox/xilinx/device-tree-xlnx
>>
>>
>> The dtbo file will not be generated without this (see "Toolflow Setup"
>> https://casper-toolflow.readthedocs.io/projects/tutorials/en/latest/tutorials/rfsoc/tut_getting_started.html
>> )
>>
>> 2) For populating the ADC information, try the "get_system_information"
>> call (fpga.get_system_information() or fpga.get_system_information('<your
>> fpg file>'))
>>
>> Cheers,
>> Jonathon
>>
>> On Thu, 8 Jun 2023 at 08:02, Cedric Viou <[email protected]>
>> wrote:
>>
>>> Hi!
>>>
>>> We are starting to use ADCs with our RFSoC4x2 and we encounter 2 related
>>> (?) problems.
>>>
>>> First, the tutorials says that we should pay attention to the generation
>>> of a .dtbo by Vivado.
>>> We can't find it after building the tutorials (and not in the
>>> jasper/vivado logs).  That was ok for tutorial 1 (RFSoC Platform ...
>>> Overview), however this seems to be mandatory for tutorial 2 (RFDC
>>> interface).
>>> Where (and how) is this supposed to be created?
>>>
>>> Then, to make some progress, we tried to use prebuilt .fpg and .dtbo
>>> from the github repository to start to use it anyway, but when the fpga is
>>> programmed with tut_rfdc, we can play with the counter and adder part, BUT
>>> we can't get information (configure, or use) about the ADC: my_RFSoC.adcs
>>> returns [].  Only my_RFSoC.listdev() returns a list of strings that
>>> contains 'rfdc', but we can't do anything with it.
>>>
>>> Any idea about what we are doing wrong?
>>>
>>> Cheers,
>>>
>>> Cedric and Nhung
>>>
>>>
>>>
>>> ###Tutorial devel
>>> commit 26fce95d9f965d7b5f5bb7c9251ca096b53272a6 (HEAD -> main,
>>> origin/main, origin/HEAD)
>>> Merge: 644f5da 81a21a1
>>> Author: Mitch Burnett <[email protected]>
>>> Date:   Thu Oct 6 17:31:31 2022 -0600
>>>
>>>
>>> ###mlib delvel
>>> commit 7f187b32133697bfdacc4fb122e9575e33acb705 (HEAD -> m2021a,
>>> origin/m2021a, origin/HEAD)
>>> Merge: 110926427 d86acbcb8
>>> Author: J. Kocz <[email protected]>
>>> Date:   Tue Oct 25 09:46:08 2022 -0700
>>>
>>> Matlab: R2021a
>>> Vivado: v2021.1 (64-bit)
>>>
>>>
>>> --
>>> Cedric Viou <[email protected]>
>>>
>>> Ingénieur de recherche
>>>
>>> Observatoire Radioastronomique de Nançay,
>>> Observatoire de Paris, PSL Research University, CNRS, Univ. Orléans,
>>> OSUC,
>>> 18330 Nançay, France
>>> http://www.obs-nancay.fr
>>>
>>> phone : +33 (0) 248 51 8609
>>>
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