Hi Tilak, I am glad to hear that you were able to use "Tutorial 3: Example Spectrometer”, and other tutorials, to test all ADC inputs of your RFSoC 4x2. That tutorial spectrometer is a good staring point for designing a spectrometer of a different resolution. Please keep in mind that changes need to be made to both the Simulink and Python codes to achieve a finer resolution spectrometer.
> (i) We tried changing the variable nfft in the above python code, but there > was no effect > (ii) Also, Change in command line the accumulation length parameter '- l ' > made no difference. Yes, there would be no effect. This is because the FFT transform size, and the sample rate, are fixed parameters in the Simulink design. The `nfft` variable in the Python code is only used to correctly interpret the output based on those fixed parameters. > (iii) To understand how it works keeping in mind that 4Gsps is the maximum > sampling rate we tried a sampling rate of 2000 Msps in the block below > ERROR: expected rfdc core axi stream clock rate 125.000 MHz on tile 224 does > not match platform selected clock > rate of 245.760 MHz. This error has occurred because the “User IP Clock Rate (MHz)” field in the RFSoC 4x2 yellow block configuration window does not match the “Required AXI4-Stream Clock (MHz)” field in the RFDC yellow block's configuration window. Before starting Vivado, the toolflow will perform a design review check (DRC) that makes sure these two fields match. The bullet you reference from Tutorial 2 is trying to explain the fact that this needs to be manually updated by the user. So, in practice after specifying the RFDC's parameters (sample rate, decimation, number of samples per clock cycle) the “Required AXI4-Stream Clock (MHz)” will be calculated and the designer needs to open the RFSoC 4x2 Yellow Block and update the “User IP Clock Rate (MHz)” filed. For you, having changed the sample rate from 3932.16 Msps to 2000 Msps, you will now will need to double-click the RFSoC 4x2 Yellow Block to open that configuration window and change the clock rate from 245.76 MHz to 125 MHz. If you alter the “Samples Per AXI4-Stream Cycle” in the RFDC mask you will need to change the “number of simultaneous input” parameters on both the PFB and FFT blocks. In the tutorial, 8 samples per cycle is chosen. That is why number of simultaneous inputs is 3 (2^3 = 8). This is also why there are 8 shared bram blocks storing accumulated FFT outputs. One block for each out the 8 samples that happen every cycle. Each Bram memory therefore stores one-eighth of the output spectrum from the FFT. If you adjust the FFT transform size will also need to alter several other components of the Simulink design. Specifically, those are: FFT shift size Vector length of the vector accumulator blocks Address width of the the shared bram memories Address counter driving the shared bram memories Sync pulse generation period (See casper pulse generation memo <https://github.com/casper-astro/publications/blob/master/Memos/files/sync_memo_v1.pdf>) Hope this helps, Mitch > On Jul 16, 2025, at 7:10 AM, Tilak Katoch <[email protected]> wrote: > > Hi Mitch, > > As per your suggestion last time, I have gone through the Tutorial 1 , 2 & 3 > for introduction to Simulink providing the details about the software and > hardware interactions. And we have succeeded in reading the input from an > external frequency synthesizer using the RFSoC 4X2 board from all the ADC > inputs using the python code "python rfsoc4x2_tut_spec.py rfsoc4x2 real" . > > Now following Tutorial 2 and 3, We are exploring ways to change the fft > sample size in order to alter/improve the frequency resolution of the > spectrometer, Δf > > (i) We tried changing the variable nfft in the above python code, but there > was no effect > (ii) Also, Change in command line the accumulation length parameter '- l ' > made no difference. > (iii) To understand how it works keeping in mind that 4Gsps is the maximum > sampling rate we tried a sampling rate of 2000 Msps in the block below > > For the RFSoC 4x2, each tile tab is configured the same with Enable Tile > selected and clock configuration set as follows.Note that the Required > AXI4-Stream Clock (MHz) field matches the clock of the RFSoC 4x2 platform > block. For a dual-tile platform configure this section as: > > > > > This gave us following error as shown below with the image > > > ERROR: expected rfdc core axi stream clock rate 125.000 MHz on tile 224 does > not match platform selected clock > rate of 245.760 MHz. > > Error using jasper (line 23) > Backend build failed! Check log files for more information > > <image.png> > > On following the Tutorial 2, it mentioned as below: > > The Required AXI4-Stream Clock field indicates what the User IP Clock Rate of > the platform yellow block must be set. There is a DRC within the toolflow > that checks to make sure the values match. However, this does require that > the CASPER designer make sure the two fields remain in sync. > > I was not able to get this thing in the program. So I need the help to set it > properly and it should reflect the change in frequency resolution. Or is > there any other way to do it, to see change in frequency resolution? > > Regards, > Tilak > > > -- > You received this message because you are subscribed to the Google Groups > "[email protected]" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected] > <mailto:[email protected]>. > To view this discussion visit > https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAPGD9M%3DxAdHN0mTyW0XnKoOiD2MizOqzq3A-sNHUZGiG3gRv_w%40mail.gmail.com > > <https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/CAPGD9M%3DxAdHN0mTyW0XnKoOiD2MizOqzq3A-sNHUZGiG3gRv_w%40mail.gmail.com?utm_medium=email&utm_source=footer>. -- You received this message because you are subscribed to the Google Groups "[email protected]" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion visit https://groups.google.com/a/lists.berkeley.edu/d/msgid/casper/1311CCA3-F790-475B-8269-E65D7075608F%40gmail.com.
