> On Aug 30, 2017, at 8:04 AM, Jerry Weiss <[email protected]> wrote: > >> >> Next you'd need some sort of bootstrap. What's in the custom EPROMs on you >> MXV11-AC might do. Or might not, depending on whether it uses any 11/23 >> (KDF-11) specific instructions or diagnostics, and includes an MSCP >> bootstrap. The autoboot feature on the UC07 might do instead. Or might >> not. You'd have to experiment. >> > > The autoboot on the UC07 uses the following instruction for the REV G > firmware. > > 200: MOV #340,@#177776 > > The memory mapped register (CSR 177776) for the processor status word (PSW) > does not exist on the LSI-11. > The purpose of this is to prevent interrupts during bootstraping from the LTC > and other devices. The processor will probably halt due to non-existent > memory address. > > However, a P entered in ODT will attempt to continue the bootstrap. If you > have and cannot disable the LTC, it may work intermittently, depending on > whether LTC interrupt occurs before he OS bootstrap loads. Its just a > matter of timing.
One clarification. The UC07 can be configured to use Power Up Option 0 on the LSI 11 (PC@24,PSW@26) too boot. This method probably avoids the problem with the manually invoked Bootstrap or FRD using an addressable PSW that some users reported.
