On 12/8/2025 6:20 PM, Van Snyder via cctalk wrote:
On Mon, 2025-12-08 at 17:49 -0600, Jay Jaeger via cctalk wrote:
2) An FPGA implementation of an IBM 1410 CPU, including tape support
(unit record will come next year, I expect), based on the original
IBM
Automated Logic Diagrams
https://www.computercollection.net/index.php/ibm-1410-fpga-implementation/
https://github.com/cube1us/IBM1410SMS
Do you plan to build an IBM 1401 also, or just use compatibility mode
in your IBM 1410?
No, I have no plans to do a 1401. That said, the ALD project and
processing application was intentionally designed to be inclusive of the
1401 SMS packaging as well as 7000 series SMS packaging, and it ought to
be less than 1/2 the work to enter the 1401 ALDs vs. the 1410. The 1401
compatibility mode on my 1410 FPGA does pass the 1410 hosted 1401 CPU
diagnostics - I haven't tried tape with it yet.
I don't remember whether the only difference between IBM 1410 and IBM
7010 was speed. If there were other differences, do you plan to build
an IBM 7010? Or if the only differences were extensions in the IBM 7010
while maintaining complete IBM 1410 compatibility, would you upgrade
your IBM 1410 to IBM 7010?
There are several differences between the 1410 and 7010. Logic families
are different, so logic levels would be as well. The 7010 can have up
to 4 channels; the 1410 is limited to two. The 7010 also has a small
feature or two that are not present in the 1410 (I would have to go look
at the 7010 Poo, but I remember Rich asking about one for which detailed
documentation was not provided in the Poo.). I have no plans to do a
7010 - for starters, I am not aware of anyone who has the ALDs for the
7010. Plus it took me about a year (elapsed) to enter the data for the
1410, and a few months to get basic stuff working in the FPGA and the
7010 would likely take even longer -- and the timing would be tighter as
well.
JRJ
