Guy, I agree that accessing data in blockram (synchronous with fixed latency) is really easier than accessing it from RAM (asynchronous with variable latency). Anyway I'm weighting the "cost" of additional complexity, which in change would allow to spare on Zynq cost. In any case memory access is never sequential, but a sequence of bursts with shorter length (16 beats or less). Considering this, the fact of starting or ending a sequential transfer is just a matter of generating addresses multiple of burst length. For this however you have to forget about Xilinx's free IP cores, and work directly with AXI3 bus of HP ports.
As I would have to invest a large amount of time and of money, it would be nice to have somebody interested in buying a working and assembled kit with moderate price gain, in way to repay part of the investment. This however drives to bottom end FPGAs, with very limited amount of internal memory... whence the memory-spare design. About documentation: you mentioned several documents about SMD/ESDI standards and related details. Would you mind sharing this collection? Many thanks. Andrea
