On 8 February 2011 21:31, Rob Landley <[email protected]> wrote: > On 02/07/2011 08:11 AM, Luke Kenneth Casson Leighton wrote: >> the SiS9561 is a dual-core 750mhz MIPS, has 1080p (unknown, at least >> p30) MPEG decode, and has PowerVR SGX. SiS have android running on >> it. pricing ... estimated... $11, maybe? possibly $10. i'm waiting >> to hear back from SiS after chinese new year, to get more info on it. >> >> basically, MIPS has traditionally been stuck in an ultra-low-cost >> rut, and it's only the simplicity of the design that has saved them >> from going under. they used to be able to afford to do their own ICs >> but were priced out of the market by the exponential jumps in NREs, >> and were forced to become a "lowly" fabless semiconductor company. > > The patent lawsuit against lexra scaring off half their customer base > probably didn't help matters: > > http://landley.net/notes-2009.html#14-12-2009 > > But I don't claim to be a mips expert, and have nothing against it. > Good luck with it if it's important to you. > >> however, as i said at http://lkcl.net/laptop.html, 45nm and 28nm >> makes even a lowly 5-stage-pipelined MIPS design scream along so fast >> that its "lowliness" is completely and utterly irrelevant, thus >> bringing it suddenly *back* into the "good enough" computing range >> (750mhz to1.5ghz), with the sudden startling advantage that its >> "lowliness" means it's cheaper and uses less power. > > Less _than_? > > Shrinking the die size helps all processors more or less equally. If it > couldn't compete against the alternatives at the previous resolution, > and the other chips are moving to the new smaller size along with it... > > I'm not seeing the game-changer here, unless the competing chips _don't_ > move to a smaller die size. Note that arm is currently working on 20 > nanometer manufacturing: > > http://skattertech.com/2010/07/arm-and-tsmc-to-work-on-20nm-process/ > >> the 64-bit core >> is only 74,000 transistors for goodness sake! > > And the arm6 core was 35,000 transistors (or at least that's Wikipedia's > opinion). And then you add enough L1 and L2 cache to the thing for > people to actualy want to use it. (How many clock cycles are we talking > to fault a cache line in from the DRAM? Moving to a smaller die size > generally doesn't do good things to that part.) > >> hence, even SiS (subsidiary of VIA) who have been stalling for ages, >> not doing any new chip designs for at least three years, suddenly took >> MIPS on-board including the PowerVR SGX block, instead of VIA's own 3D >> graphics engine(s)! >> >> lots of other companies are doing this kind of math, which places >> PowerVR SGX squarely into a position of prominence (as if intel's use >> of it for poulsbo GMA500 wasn't enough, with well over a hundred >> separate laptop designs using it). hence the importance of getting a >> free software engine off the ground, for PowerVR SGX. > > Good luck with that. > > I continue to not actually be _excited_ by this, but perhaps I'm missing > something. I'll continue to support mips in aboriginal linux (and am > working on adding a target for that new mips instruction set thingy > mentioned at http://www.mips.com/products/architectures/mips32/ which > Vladimir Dronnikov bumped into in a TV he's porting Linux to, although > QEMU still doesn't seem to support that yet so I can't test it).
Kind of unrelated, but what exactly isn't supported by QEMU? MIPS32 seems to be supported according to: http://www.linux-mips.org/wiki/Qemu --lf > > But "importance" still seems a bit strong to me... > > Rob > _______________________________________________ > Celinux-dev mailing list > [email protected] > http://tree.celinuxforum.org/mailman/listinfo/celinux-dev > -- Luís Felipe Strano Moraes ProFUSION embedded systems http://profusion.mobi _______________________________________________ Celinux-dev mailing list [email protected] http://tree.celinuxforum.org/mailman/listinfo/celinux-dev
