efriedma added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1220
+void AArch64DAGToDAGISel::SelectTableSVE2(SDNode *N, unsigned Opc) {
+ SDLoc DL(N);
----------------
Is it possible to write this as a TableGen pattern? We manage for other
variants of tbl (for example,
https://github.com/llvm/llvm-project/blob/bc7b26c333f51b4b534abb81d597c0b86123718c/llvm/lib/Target/ARM/ARMInstrNEON.td#L7059
).
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D74912/new/
https://reviews.llvm.org/D74912
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