evandro added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:56 +def NoConstraint : RISCVVConstraint<0>; +def WidenV : RISCVVConstraint<1>; +def WidenW : RISCVVConstraint<2>; ---------------- Methinks that these constraints `WidenV`, `WidenW`, `WidenCvt`, should be split up by their components. IOW, into `Widen`, `Wide` (input), `Cvt`. This way, it's easier to test for specific constraints. ================ Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:61 +def Narrow : RISCVVConstraint<5>; +def NarrowCvt : RISCVVConstraint<6>; +def Iota : RISCVVConstraint<7>; ---------------- Likewise, this constraint could then be removed, but `Narrow && Cvt` would achieve the same meaning. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D69987/new/ https://reviews.llvm.org/D69987 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
