Author: jacquesguan Date: 2021-12-20T14:25:06+08:00 New Revision: 9c11e952868342dfbf0efedd246dac6191ee98d7
URL: https://github.com/llvm/llvm-project/commit/9c11e952868342dfbf0efedd246dac6191ee98d7 DIFF: https://github.com/llvm/llvm-project/commit/9c11e952868342dfbf0efedd246dac6191ee98d7.diff LOG: [Clang][RISCV] Fix upper bound of RISC-V V type in debug info The UpperBound of RVV type in debug info should be elements count minus one, as the LowerBound start from zero. Reviewed By: HsiangKai Differential Revision: https://reviews.llvm.org/D115430 Added: Modified: clang/lib/CodeGen/CGDebugInfo.cpp clang/test/CodeGen/RISCV/riscv-v-debuginfo.c Removed: ################################################################################ diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp index 0de089b448093..89ec9f1b7e8fd 100644 --- a/clang/lib/CodeGen/CGDebugInfo.cpp +++ b/clang/lib/CodeGen/CGDebugInfo.cpp @@ -768,7 +768,7 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType *BT) { } // Element count = (VLENB / SEW) x LMUL - SmallVector<int64_t, 9> Expr( + SmallVector<int64_t, 12> Expr( // The DW_OP_bregx operation has two operands: a register which is // specified by an unsigned LEB128 number, followed by a signed LEB128 // offset. @@ -782,6 +782,8 @@ llvm::DIType *CGDebugInfo::CreateType(const BuiltinType *BT) { Expr.push_back(llvm::dwarf::DW_OP_div); else Expr.push_back(llvm::dwarf::DW_OP_mul); + // Element max index = count - 1 + Expr.append({llvm::dwarf::DW_OP_constu, 1, llvm::dwarf::DW_OP_minus}); auto *LowerBound = llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSigned( diff --git a/clang/test/CodeGen/RISCV/riscv-v-debuginfo.c b/clang/test/CodeGen/RISCV/riscv-v-debuginfo.c index b5ed0c56848b1..f0e405aa79c66 100644 --- a/clang/test/CodeGen/RISCV/riscv-v-debuginfo.c +++ b/clang/test/CodeGen/RISCV/riscv-v-debuginfo.c @@ -9,7 +9,7 @@ __rvv_int16m2_t f1(__rvv_int16m2_t arg_0, __rvv_int16m2_t arg_1, int64_t arg_2) } // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con -// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul)) +// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus)) __rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t arg_2) { __rvv_int16mf2_t ret; @@ -17,7 +17,7 @@ __rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t arg_ } // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con -// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div)) +// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus)) __rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t arg_2) { __rvv_int32mf2_t ret; @@ -25,4 +25,4 @@ __rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t arg_ } // !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con -// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div)) +// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 1, DW_OP_minus)) _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
