craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1499
foreach nf=2-8 in {
+ // Vector Unit-strided Segment Instructions
+ def VLSEG#nf#E64_V :
----------------
The unit-stride and strided with EEW=64 don't require RV64. Just the indexed
versions.
================
Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:193
+ bool hasVInstructionsF16() const { return HasStdExtZve32x && HasStdExtZfh; }
+ bool hasVInstructionsF32() const { return HasStdExtF && HasStdExtZve32x; }
+ bool hasVInstructionsF64() const { return HasStdExtD && HasStdExtZve64x; }
----------------
This needs to check Zve32f not Zve32x I think?
================
Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:194
+ bool hasVInstructionsF32() const { return HasStdExtF && HasStdExtZve32x; }
+ bool hasVInstructionsF64() const { return HasStdExtD && HasStdExtZve64x; }
// F16 and F64 both require F32.
----------------
This should check Zve64d not Zve64x I think?
================
Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.h:196
// F16 and F64 both require F32.
- bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
+ bool hasVInstructionsAnyF() const { return HasStdExtF && HasStdExtZve32x; }
unsigned getMaxInterleaveFactor() const {
----------------
Leave this line as an alias to hasVInstructionsF32()
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D112408/new/
https://reviews.llvm.org/D112408
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