achieveartificialintelligence added inline comments.
================ Comment at: llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll:2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+zfh \ +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64d,+f,+d,+zfh \ ; RUN: -verify-machineinstrs < %s | FileCheck %s ---------------- Do we need `+f` here? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112408/new/ https://reviews.llvm.org/D112408 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
