This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
amyk marked an inline comment as done.
Closed by commit rG2534dc120a4c: [PowerPC] Enable CR bits support for Power8
and above. (authored by amyk).
Changed prior to commit:
https://reviews.llvm.org/D124060?vs=425417&id=426439#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D124060/new/
https://reviews.llvm.org/D124060
Files:
clang/docs/ClangCommandLineReference.rst
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Driver/ppc-crbits.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/test/CodeGen/PowerPC/addegluecrash.ll
llvm/test/CodeGen/PowerPC/f128-branch-cond.ll
llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
Index: llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
+++ llvm/test/CodeGen/PowerPC/pcrel-byte-loads.ll
@@ -45,6 +45,7 @@
; CHECK-LE-LABEL: i32_ZextLoad_i1:
; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT: clrldi r3, r3, 63
; CHECK-LE-NEXT: pstb r3, GlobSt1@PCREL(0), 1
; CHECK-LE-NEXT: blr
;
@@ -53,6 +54,7 @@
; CHECK-BE-NEXT: addis r3, r2, GlobLd1@toc@ha
; CHECK-BE-NEXT: addis r4, r2, GlobSt1@toc@ha
; CHECK-BE-NEXT: lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT: clrldi r3, r3, 63
; CHECK-BE-NEXT: stb r3, GlobSt1@toc@l(r4)
; CHECK-BE-NEXT: blr
entry:
@@ -77,11 +79,11 @@
; CHECK-LE-NEXT: paddi r3, 0, Glob1@PCREL, 1
; CHECK-LE-NEXT: paddi r4, 0, Glob2@PCREL, 1
; CHECK-LE-NEXT: bl Decl@notoc
-; CHECK-LE-NEXT: plbz r4, GlobLd1@PCREL(0), 1
-; CHECK-LE-NEXT: cmplwi r3, 0
-; CHECK-LE-NEXT: li r3, 1
-; CHECK-LE-NEXT: iseleq r3, 0, r3
-; CHECK-LE-NEXT: and r3, r3, r4
+; CHECK-LE-NEXT: cmpwi cr1, r3, 0
+; CHECK-LE-NEXT: plbz r3, GlobLd1@PCREL(0), 1
+; CHECK-LE-NEXT: andi. r3, r3, 1
+; CHECK-LE-NEXT: crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-LE-NEXT: setbc r3, 4*cr5+lt
; CHECK-LE-NEXT: addi r1, r1, 32
; CHECK-LE-NEXT: ld r0, 16(r1)
; CHECK-LE-NEXT: mtlr r0
@@ -100,12 +102,12 @@
; CHECK-BE-NEXT: addi r4, r4, Glob2@toc@l
; CHECK-BE-NEXT: bl Decl
; CHECK-BE-NEXT: nop
-; CHECK-BE-NEXT: addis r4, r2, GlobLd1@toc@ha
-; CHECK-BE-NEXT: cmplwi r3, 0
-; CHECK-BE-NEXT: li r3, 1
-; CHECK-BE-NEXT: lbz r4, GlobLd1@toc@l(r4)
-; CHECK-BE-NEXT: iseleq r3, 0, r3
-; CHECK-BE-NEXT: and r3, r3, r4
+; CHECK-BE-NEXT: cmpwi cr1, r3, 0
+; CHECK-BE-NEXT: addis r3, r2, GlobLd1@toc@ha
+; CHECK-BE-NEXT: lbz r3, GlobLd1@toc@l(r3)
+; CHECK-BE-NEXT: andi. r3, r3, 1
+; CHECK-BE-NEXT: crandc 4*cr5+lt, gt, 4*cr1+eq
+; CHECK-BE-NEXT: setbc r3, 4*cr5+lt
; CHECK-BE-NEXT: addi r1, r1, 112
; CHECK-BE-NEXT: ld r0, 16(r1)
; CHECK-BE-NEXT: mtlr r0
Index: llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
+++ llvm/test/CodeGen/PowerPC/fp64-to-int16.ll
@@ -7,11 +7,11 @@
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws 0, 1
; CHECK-NEXT: mffprwz 3, 0
-; CHECK-NEXT: xori 3, 3, 65534
-; CHECK-NEXT: cntlzw 3, 3
-; CHECK-NEXT: srwi 4, 3, 5
-; CHECK-NEXT: # implicit-def: $x3
-; CHECK-NEXT: mr 3, 4
+; CHECK-NEXT: cmplwi 3, 65534
+; CHECK-NEXT: crmove 20, 2
+; CHECK-NEXT: li 4, 0
+; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: isel 3, 3, 4, 20
; CHECK-NEXT: blr
entry:
%conv = fptoui double %a to i16
Index: llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
+++ llvm/test/CodeGen/PowerPC/fp-strict-fcmp-noopt.ll
@@ -5,25 +5,19 @@
define i32 @une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; CHECK-LABEL: une_ppcf128:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscmpudp cr7, f1, f3
-; CHECK-NEXT: mfocrf r3, 1
-; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT: xscmpudp cr7, f2, f4
-; CHECK-NEXT: mfocrf r4, 1
-; CHECK-NEXT: rlwinm r4, r4, 31, 31, 31
-; CHECK-NEXT: xori r4, r4, 1
-; CHECK-NEXT: and r4, r3, r4
-; CHECK-NEXT: xscmpudp cr7, f1, f3
-; CHECK-NEXT: mfocrf r3, 1
-; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: xscmpudp cr7, f1, f3
-; CHECK-NEXT: mfocrf r5, 1
-; CHECK-NEXT: rlwinm r5, r5, 31, 31, 31
-; CHECK-NEXT: xori r5, r5, 1
-; CHECK-NEXT: and r3, r3, r5
-; CHECK-NEXT: or r3, r3, r4
-; CHECK-NEXT: # kill: def $r4 killed $r3
+; CHECK-NEXT: fcmpu cr0, f1, f3
+; CHECK-NEXT: crmove 4*cr5+lt, eq
+; CHECK-NEXT: fcmpu cr1, f2, f4
+; CHECK-NEXT: crmove 4*cr5+gt, 4*cr1+eq
+; CHECK-NEXT: crnot 4*cr5+gt, 4*cr5+gt
+; CHECK-NEXT: crand 4*cr5+gt, 4*cr5+lt, 4*cr5+gt
+; CHECK-NEXT: crmove 4*cr5+lt, eq
+; CHECK-NEXT: crnot 4*cr5+lt, 4*cr5+lt
+; CHECK-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+lt
+; CHECK-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; CHECK-NEXT: li r4, 0
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@@ -36,28 +30,19 @@
define i32 @ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {
; CHECK-LABEL: ogt_ppcf128:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscmpudp cr7, f1, f3
-; CHECK-NEXT: mfocrf r3, 1
-; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT: xscmpudp cr7, f2, f4
-; CHECK-NEXT: mfocrf r4, 1
-; CHECK-NEXT: rlwinm r4, r4, 30, 31, 31
-; CHECK-NEXT: and r4, r3, r4
-; CHECK-NEXT: xscmpudp cr0, f1, f3
-; CHECK-NEXT: mfocrf r3, 128
-; CHECK-NEXT: stw r3, -4(r1)
-; CHECK-NEXT: xscmpudp cr7, f1, f3
-; CHECK-NEXT: mfocrf r3, 1
-; CHECK-NEXT: lwz r5, -4(r1)
-; CHECK-NEXT: rotlwi r5, r5, 4
-; CHECK-NEXT: mtocrf 1, r5
-; CHECK-NEXT: rlwinm r5, r3, 30, 31, 31
-; CHECK-NEXT: mfocrf r3, 1
-; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT: xori r3, r3, 1
-; CHECK-NEXT: and r3, r3, r5
-; CHECK-NEXT: or r3, r3, r4
-; CHECK-NEXT: # kill: def $r4 killed $r3
+; CHECK-NEXT: fcmpu cr0, f1, f3
+; CHECK-NEXT: crmove 4*cr5+lt, eq
+; CHECK-NEXT: fcmpu cr1, f2, f4
+; CHECK-NEXT: crmove 4*cr5+gt, 4*cr1+gt
+; CHECK-NEXT: crand 4*cr5+gt, 4*cr5+lt, 4*cr5+gt
+; CHECK-NEXT: crmove 4*cr5+lt, eq
+; CHECK-NEXT: crnot 4*cr5+lt, 4*cr5+lt
+; CHECK-NEXT: crmove 4*cr5+eq, gt
+; CHECK-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+eq
+; CHECK-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; CHECK-NEXT: li r4, 0
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt
; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr
entry:
@@ -69,12 +54,14 @@
define i1 @test_f128(fp128 %a, fp128 %b) #0 {
; CHECK-LABEL: test_f128:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscmpuqp cr7, v2, v3
-; CHECK-NEXT: mfocrf r3, 1
-; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT: xori r4, r3, 1
-; CHECK-NEXT: # implicit-def: $x3
-; CHECK-NEXT: mr r3, r4
+; CHECK-NEXT: xscmpuqp cr0, v2, v3
+; CHECK-NEXT: crmove 4*cr5+lt, eq
+; CHECK-NEXT: xscmpuqp cr0, v2, v3
+; CHECK-NEXT: crmove 4*cr5+gt, eq
+; CHECK-NEXT: crnor 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
+; CHECK-NEXT: li r4, 0
+; CHECK-NEXT: li r3, 1
+; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt
; CHECK-NEXT: blr
entry:
%0 = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"une", metadata !"fpexcept.strict") #0
@@ -84,11 +71,9 @@
define i1 @testbr_f64(double %a, double %b) #0 {
; CHECK-LABEL: testbr_f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xscmpudp cr7, f1, f2
-; CHECK-NEXT: mfocrf r3, 1
-; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT: cmplwi r3, 0
-; CHECK-NEXT: bne cr0, .LBB3_2
+; CHECK-NEXT: fcmpu cr0, f1, f2
+; CHECK-NEXT: crmove 4*cr5+lt, eq
+; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB3_2
; CHECK-NEXT: b .LBB3_1
; CHECK-NEXT: .LBB3_1: # %tr
; CHECK-NEXT: li r3, -1
@@ -108,11 +93,9 @@
define i1 @testbr_f32(float %a, float %b) #0 {
; CHECK-LABEL: testbr_f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: fcmpu cr7, f1, f2
-; CHECK-NEXT: mfocrf r3, 1
-; CHECK-NEXT: rlwinm r3, r3, 31, 31, 31
-; CHECK-NEXT: cmplwi r3, 0
-; CHECK-NEXT: bne cr0, .LBB4_2
+; CHECK-NEXT: fcmpu cr0, f1, f2
+; CHECK-NEXT: crmove 4*cr5+lt, eq
+; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB4_2
; CHECK-NEXT: b .LBB4_1
; CHECK-NEXT: .LBB4_1: # %tr
; CHECK-NEXT: li r3, -1
Index: llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
+++ llvm/test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll
@@ -2,7 +2,7 @@
define i1 @TestULT(double %t0) {
; CHECK-LABEL: TestULT:
-; CHECK: xscmpudp
+; CHECK: fcmpu
; CHECK: blr
entry:
%t1 = fcmp ult double %t0, 0.000000e+00
@@ -49,7 +49,7 @@
define i1 @TestUEQ(double %t0) {
; CHECK-LABEL: TestUEQ:
-; CHECK: xscmpudp
+; CHECK: fcmpu
; CHECK: blr
entry:
%t1 = fcmp ueq double %t0, 0.000000e+00
@@ -64,7 +64,7 @@
define i1 @TestUGT(double %t0) {
; CHECK-LABEL: TestUGT:
-; CHECK: xscmpudp
+; CHECK: fcmpu
; CHECK: blr
entry:
%t1 = fcmp ugt double %t0, 0.000000e+00
@@ -111,7 +111,7 @@
define i1 @TestOLE(double %t0) {
; CHECK-LABEL: TestOLE:
-; CHECK: xscmpudp
+; CHECK: fcmpu
; CHECK: blr
entry:
%t1 = fcmp ole double %t0, 0.000000e+00
@@ -126,7 +126,7 @@
define i1 @TestONE(double %t0) {
; CHECK-LABEL: TestONE:
-; CHECK: xscmpudp
+; CHECK: fcmpu
; CHECK: blr
entry:
%t1 = fcmp one double %t0, 0.000000e+00
@@ -173,7 +173,7 @@
define i1 @TestOGE(double %t0) {
; CHECK-LABEL: TestOGE:
-; CHECK: xscmpudp
+; CHECK: fcmpu
; CHECK: blr
entry:
%t1 = fcmp oge double %t0, 0.000000e+00
Index: llvm/test/CodeGen/PowerPC/f128-branch-cond.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/f128-branch-cond.ll
+++ llvm/test/CodeGen/PowerPC/f128-branch-cond.ll
@@ -14,10 +14,6 @@
; P8-NEXT: nop
; P8-NEXT: # kill: def $r3 killed $r3 killed $x3
; P8-NEXT: cmplwi 3, 0
-; P8-NEXT: li 3, 0
-; P8-NEXT: li 4, 1
-; P8-NEXT: iseleq 3, 3, 4
-; P8-NEXT: cmplwi 3, 0
; P8-NEXT: bne 0, .LBB0_2
; P8-NEXT: b .LBB0_1
; P8-NEXT: .LBB0_1: # %if.true
@@ -88,11 +84,7 @@
; P8-NEXT: nop
; P8-NEXT: # kill: def $r3 killed $r3 killed $x3
; P8-NEXT: cmpwi 3, 1
-; P8-NEXT: li 4, 0
-; P8-NEXT: li 3, 1
-; P8-NEXT: isellt 3, 3, 4
-; P8-NEXT: cmplwi 3, 0
-; P8-NEXT: bne 0, .LBB1_2
+; P8-NEXT: blt 0, .LBB1_2
; P8-NEXT: b .LBB1_1
; P8-NEXT: .LBB1_1: # %if.true
; P8-NEXT: bl foo
@@ -115,37 +107,30 @@
; P9: # %bb.0: # %entry
; P9-NEXT: mflr 0
; P9-NEXT: std 0, 16(1)
-; P9-NEXT: stdu 1, -128(1)
-; P9-NEXT: xscmpuqp 7, 2, 3
-; P9-NEXT: mfocrf 3, 1
-; P9-NEXT: rotlwi 3, 3, 28
-; P9-NEXT: stw 3, 124(1)
-; P9-NEXT: mfocrf 3, 1
-; P9-NEXT: lwz 4, 124(1)
-; P9-NEXT: rotlwi 4, 4, 4
-; P9-NEXT: mtocrf 1, 4
-; P9-NEXT: clrlwi 3, 3, 31
-; P9-NEXT: xori 4, 3, 1
-; P9-NEXT: mfocrf 3, 1
-; P9-NEXT: rlwinm 3, 3, 30, 31, 31
-; P9-NEXT: xori 3, 3, 1
-; P9-NEXT: and 3, 3, 4
-; P9-NEXT: cmplwi 3, 0
-; P9-NEXT: bne 0, .LBB1_2
+; P9-NEXT: stdu 1, -112(1)
+; P9-NEXT: xscmpuqp 0, 2, 3
+; P9-NEXT: crmove 20, 3
+; P9-NEXT: crnot 21, 20
+; P9-NEXT: crmove 20, 1
+; P9-NEXT: crnot 20, 20
+; P9-NEXT: crand 20, 20, 21
+; P9-NEXT: crxor 21, 21, 21
+; P9-NEXT: crxor 20, 20, 21
+; P9-NEXT: bc 12, 20, .LBB1_2
; P9-NEXT: b .LBB1_1
; P9-NEXT: .LBB1_1: # %if.true
; P9-NEXT: bl foo
; P9-NEXT: nop
-; P9-NEXT: stw 3, 120(1) # 4-byte Folded Spill
+; P9-NEXT: stw 3, 108(1) # 4-byte Folded Spill
; P9-NEXT: b .LBB1_3
; P9-NEXT: .LBB1_2: # %if.false
; P9-NEXT: bl bar
; P9-NEXT: nop
-; P9-NEXT: stw 3, 120(1) # 4-byte Folded Spill
+; P9-NEXT: stw 3, 108(1) # 4-byte Folded Spill
; P9-NEXT: .LBB1_3: # %final
-; P9-NEXT: lwz 3, 120(1) # 4-byte Folded Reload
+; P9-NEXT: lwz 3, 108(1) # 4-byte Folded Reload
; P9-NEXT: clrldi 3, 3, 32
-; P9-NEXT: addi 1, 1, 128
+; P9-NEXT: addi 1, 1, 112
; P9-NEXT: ld 0, 16(1)
; P9-NEXT: mtlr 0
; P9-NEXT: blr
@@ -175,10 +160,8 @@
; P8-NEXT: bl __ltkf2
; P8-NEXT: nop
; P8-NEXT: # kill: def $r3 killed $r3 killed $x3
-; P8-NEXT: not 3, 3
-; P8-NEXT: srwi 3, 3, 31
-; P8-NEXT: cmplwi 3, 0
-; P8-NEXT: bne 0, .LBB2_2
+; P8-NEXT: cmpwi 3, -1
+; P8-NEXT: bgt 0, .LBB2_2
; P8-NEXT: b .LBB2_1
; P8-NEXT: .LBB2_1: # %if.true
; P8-NEXT: bl foo
Index: llvm/test/CodeGen/PowerPC/addegluecrash.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/addegluecrash.ll
+++ llvm/test/CodeGen/PowerPC/addegluecrash.ll
@@ -23,12 +23,11 @@
; CHECK-NEXT: addc 6, 6, 7
; CHECK-NEXT: addze 5, 5
; CHECK-NEXT: add 3, 5, 3
-; CHECK-NEXT: cmpld 7, 3, 5
-; CHECK-NEXT: mfocrf 3, 1
-; CHECK-NEXT: rlwinm 5, 3, 29, 31, 31
-; CHECK-NEXT: # implicit-def: $x3
-; CHECK-NEXT: mr 3, 5
-; CHECK-NEXT: clrldi 3, 3, 32
+; CHECK-NEXT: cmpld 3, 5
+; CHECK-NEXT: crmove 20, 0
+; CHECK-NEXT: li 5, 0
+; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: isel 3, 3, 5, 20
; CHECK-NEXT: std 3, 0(4)
; CHECK-NEXT: blr
%1 = load i64, i64* %a, align 8
Index: llvm/lib/Target/PowerPC/PPC.td
===================================================================
--- llvm/lib/Target/PowerPC/PPC.td
+++ llvm/lib/Target/PowerPC/PPC.td
@@ -376,7 +376,8 @@
FeaturePartwordAtomic,
FeatureQuadwordAtomic,
FeaturePredictableSelectIsExpensive,
- FeatureISA2_07
+ FeatureISA2_07,
+ FeatureCRBits
];
list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion,
Index: clang/test/Driver/ppc-crbits.cpp
===================================================================
--- /dev/null
+++ clang/test/Driver/ppc-crbits.cpp
@@ -0,0 +1,112 @@
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr10 \
+// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr10 \
+// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr9 \
+// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr9 \
+// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr8 \
+// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr8 \
+// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr7 \
+// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
+// RUN: %clang -target powerpc64le-unknown-linux-gnu %s -### -mcpu=pwr7 \
+// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
+
+// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr10 \
+// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
+// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr10 \
+// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
+
+// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr9 \
+// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
+// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr9 \
+// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
+
+// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr8 \
+// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
+// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr8 \
+// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
+
+// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr7 \
+// RUN: -mcrbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-CRBITS %s
+// RUN: %clang -target powerpc-ibm-aix %s -### -mcpu=pwr7 \
+// RUN: -mno-crbits -o %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOCRBITS %s
+
+
+// CHECK-NOCRBITS: "-target-feature" "-crbits"
+// CHECK-CRBITS: "-target-feature" "+crbits"
+
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -emit-llvm \
+// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -mcrbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -mno-crbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr9 -emit-llvm \
+// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr9 -mcrbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr9 -mno-crbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -emit-llvm \
+// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mcrbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mno-crbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -emit-llvm \
+// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -mcrbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -mno-crbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr10 -emit-llvm \
+// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr10 -mcrbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr10 -mno-crbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr9 -emit-llvm \
+// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr9 -mcrbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr9 -mno-crbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr8 -emit-llvm \
+// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr8 -mcrbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr8 -mno-crbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -emit-llvm \
+// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -mcrbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
+// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -mno-crbits \
+// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
+
+
+// HAS-CRBITS: main(
+// HAS-CRBITS: attributes #0 = {
+// HAS-CRBITS-SAME: +crbits
+// HAS-NOCRBITS: main(
+// HAS-NOCRBITS: attributes #0 = {
+// HAS-NOCRBITS-SAME: -crbits
+
+int main(int argc, char *argv[]) {
+ return 0;
+}
Index: clang/lib/Basic/Targets/PPC.h
===================================================================
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -62,6 +62,7 @@
bool HasROPProtect = false;
bool HasPrivileged = false;
bool HasVSX = false;
+ bool UseCRBits = false;
bool HasP8Vector = false;
bool HasP8Crypto = false;
bool HasDirectMove = false;
Index: clang/lib/Basic/Targets/PPC.cpp
===================================================================
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -36,6 +36,8 @@
HasAltivec = true;
} else if (Feature == "+vsx") {
HasVSX = true;
+ } else if (Feature == "+crbits") {
+ UseCRBits = true;
} else if (Feature == "+bpermd") {
HasBPERMD = true;
} else if (Feature == "+extdiv") {
@@ -515,6 +517,11 @@
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);
+ Features["crbits"] = llvm::StringSwitch<bool>(CPU)
+ .Case("ppc64le", true)
+ .Case("pwr9", true)
+ .Case("pwr8", true)
+ .Default(false);
Features["vsx"] = llvm::StringSwitch<bool>(CPU)
.Case("ppc64le", true)
.Case("pwr9", true)
@@ -649,6 +656,7 @@
.Case("powerpc", true)
.Case("altivec", HasAltivec)
.Case("vsx", HasVSX)
+ .Case("crbits", UseCRBits)
.Case("power8-vector", HasP8Vector)
.Case("crypto", HasP8Crypto)
.Case("direct-move", HasDirectMove)
Index: clang/docs/ClangCommandLineReference.rst
===================================================================
--- clang/docs/ClangCommandLineReference.rst
+++ clang/docs/ClangCommandLineReference.rst
@@ -3575,6 +3575,8 @@
.. option:: -mcrbits, -mno-crbits
+Control the CR-bit tracking feature on PowerPC. ``-mcrbits`` (the enablement of CR-bit tracking support) is the default for POWER8 and above, as well as for all other CPUs when optimization is applied (-O2 and above).
+
.. option:: -mcrypto, -mno-crypto
.. option:: -mdirect-move, -mno-direct-move
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