jhuber6 added a comment.

I made the phases always go to `Assemble` but it didn't make a difference. We 
still get the textual IR here without the exception I added.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141717/new/

https://reviews.llvm.org/D141717

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