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Ignoring freeze(undef) if it has multiple uses in LowerAVXCONCAT_VECTORS causes 
the custom INSERT_SUBVECTOR for vector widening to be ignored.

For example in https://godbolt.org/z/7hacPe1KM extra vinsertf128 instructions 
are introduced.

This is necessary to lower `mm512_cast*128` intel intrinsics as no-op 
intrinsics.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D144903

Files:
  clang/test/CodeGen/X86/avx-cast-builtins.c
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/avx512-intrinsics.ll
  llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll

Index: llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
===================================================================
--- llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
+++ llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll
@@ -1231,10 +1231,7 @@
 define <32 x half> @test_mm512_castph128_ph512_freeze(<8 x half> %a0) nounwind {
 ; CHECK-LABEL: test_mm512_castph128_ph512_freeze:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm1
-; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; CHECK-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
 ; CHECK-NEXT:    retq
   %a1 = freeze <8 x half> poison
   %res = shufflevector <8 x half> %a0, <8 x half> %a1, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
Index: llvm/test/CodeGen/X86/avx512-intrinsics.ll
===================================================================
--- llvm/test/CodeGen/X86/avx512-intrinsics.ll
+++ llvm/test/CodeGen/X86/avx512-intrinsics.ll
@@ -7495,10 +7495,7 @@
 define <8 x double> @test_mm256_castpd128_pd256_freeze(<2 x double> %a0) nounwind {
 ; CHECK-LABEL: test_mm256_castpd128_pd256_freeze:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm1
-; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; CHECK-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
 ; CHECK-NEXT:    ret{{[l|q]}}
   %a1 = freeze <2 x double> poison
   %res = shufflevector <2 x double> %a0, <2 x double> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
@@ -7520,10 +7517,7 @@
 define <16 x float> @test_mm256_castps128_ps512_freeze(<4 x float> %a0) nounwind {
 ; CHECK-LABEL: test_mm256_castps128_ps512_freeze:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm1
-; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; CHECK-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
 ; CHECK-NEXT:    ret{{[l|q]}}
   %a1 = freeze <4 x float> poison
   %res = shufflevector <4 x float> %a0, <4 x float> %a1, <16x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
@@ -7545,10 +7539,7 @@
 define <8 x i64> @test_mm512_castsi128_si512_freeze(<2 x i64> %a0) nounwind {
 ; CHECK-LABEL: test_mm512_castsi128_si512_freeze:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm1
-; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
-; CHECK-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
 ; CHECK-NEXT:    ret{{[l|q]}}
   %a1 = freeze <2 x i64> poison
   %res = shufflevector <2 x i64> %a0, <2 x i64> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 2, i32 3>
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -11656,7 +11656,7 @@
     SDValue SubVec = Op.getOperand(i);
     if (SubVec.isUndef())
       continue;
-    if (ISD::isFreezeUndef(SubVec.getNode()) && SubVec.hasOneUse())
+    if (ISD::isFreezeUndef(SubVec.getNode()))
       ++NumFreezeUndef;
     else if (ISD::isBuildVectorAllZeros(SubVec.getNode()))
       ++NumZero;
Index: clang/test/CodeGen/X86/avx-cast-builtins.c
===================================================================
--- clang/test/CodeGen/X86/avx-cast-builtins.c
+++ clang/test/CodeGen/X86/avx-cast-builtins.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 %s -O3 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +avx -target-feature +avx512f  -target-feature +avx512fp16 -S -o - | FileCheck %s
+// RUN: %clang_cc1 %s -O3  -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +avx -target-feature +avx512f  -target-feature +avx512fp16 -S -o - | FileCheck %s
 
 
 #include <immintrin.h>
@@ -38,10 +38,7 @@
 __m512h test_mm512_castph128_ph512(__m128h A) {
   // CHECK-LABEL: test_mm512_castph128_ph512
   // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-  // CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm1
-  // CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
-  // CHECK-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
   // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castph128_ph512(A);
 }
@@ -73,10 +70,7 @@
 __m512d test_mm512_castpd128_pd512(__m128d A){
   // CHECK-LABEL: test_mm512_castpd128_pd512
   // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-  // CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm1
-  // CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
-  // CHECK-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
   // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castpd128_pd512(A);
 }
@@ -84,10 +78,7 @@
 __m512 test_mm512_castps128_ps512(__m128 A){
   // CHECK-LABEL: test_mm512_castps128_ps512
   // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-  // CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm1
-  // CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
-  // CHECK-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
   // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castps128_ps512(A);
 }
@@ -95,10 +86,7 @@
 __m512i test_mm512_castsi128_si512(__m128i A){
   // CHECK-LABEL: test_mm512_castsi128_si512
   // CHECK:         # %bb.0:
-  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
-  // CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm1
-  // CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
-  // CHECK-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+  // CHECK-NEXT:    # kill: def $xmm0 killed $xmm0 def $zmm0
   // CHECK-NEXT:    ret{{[l|q]}}
   return _mm512_castsi128_si512(A);
 }
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