sstwcw created this revision.
sstwcw added reviewers: HazardyKnusperkeks, MyDeveloperDay, owenpan, rymiel.
Herald added a project: All.
sstwcw requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D146402
Files:
clang/lib/Format/FormatToken.h
clang/lib/Format/TokenAnnotator.cpp
clang/unittests/Format/FormatTestVerilog.cpp
Index: clang/unittests/Format/FormatTestVerilog.cpp
===================================================================
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -97,6 +97,23 @@
Style);
}
+TEST_F(FormatTestVerilog, Assign) {
+ verifyFormat("assign mynet = enable;");
+ verifyFormat("assign (strong1, pull0) #1 mynet = enable;");
+ verifyFormat("assign #1 mynet = enable;");
+ verifyFormat("assign mynet = enable;");
+ // Test that assignments are on separate lines.
+ verifyFormat("assign mynet = enable,\n"
+ " mynet1 = enable1;");
+ // Test that `<=` and `,` don't confuse it.
+ verifyFormat("assign mynet = enable1 <= enable2;");
+ verifyFormat("assign mynet = enable1 <= enable2,\n"
+ " mynet1 = enable3;");
+ verifyFormat("assign mynet = enable,\n"
+ " mynet1 = enable2 <= enable3;");
+ verifyFormat("assign mynet = enable(enable1, enable2);");
+}
+
TEST_F(FormatTestVerilog, BasedLiteral) {
verifyFormat("x = '0;");
verifyFormat("x = '1;");
Index: clang/lib/Format/TokenAnnotator.cpp
===================================================================
--- clang/lib/Format/TokenAnnotator.cpp
+++ clang/lib/Format/TokenAnnotator.cpp
@@ -1284,8 +1284,11 @@
Tok->setType(TT_InheritanceComma);
break;
default:
- if (Contexts.back().FirstStartOfName &&
- (Contexts.size() == 1 || startsWithInitStatement(Line))) {
+ if (Style.isVerilog() && Contexts.size() == 1 &&
+ Line.startsWith(Keywords.kw_assign)) {
+ Tok->setFinalizedType(TT_VerilogAssignComma);
+ } else if (Contexts.back().FirstStartOfName &&
+ (Contexts.size() == 1 || startsWithInitStatement(Line))) {
Contexts.back().FirstStartOfName->PartOfMultiVariableDeclStmt = true;
Line.IsMultiVariableDeclStmt = true;
}
@@ -4689,6 +4692,9 @@
return true;
}
} else if (Style.isVerilog()) {
+ // Break between assignments.
+ if (Left.is(TT_VerilogAssignComma))
+ return true;
// Break between ports of different types.
if (Left.is(TT_VerilogTypeComma))
return true;
Index: clang/lib/Format/FormatToken.h
===================================================================
--- clang/lib/Format/FormatToken.h
+++ clang/lib/Format/FormatToken.h
@@ -144,6 +144,8 @@
TYPE(UnaryOperator)
\
TYPE(UnionLBrace)
\
TYPE(UntouchableMacroFunc)
\
+ /* Like in 'assign x = 0, y = 1;' . */
\
+ TYPE(VerilogAssignComma)
\
/* like in begin : block */
\
TYPE(VerilogBlockLabelColon)
\
/* The square bracket for the dimension part of the type name.
\
Index: clang/unittests/Format/FormatTestVerilog.cpp
===================================================================
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -97,6 +97,23 @@
Style);
}
+TEST_F(FormatTestVerilog, Assign) {
+ verifyFormat("assign mynet = enable;");
+ verifyFormat("assign (strong1, pull0) #1 mynet = enable;");
+ verifyFormat("assign #1 mynet = enable;");
+ verifyFormat("assign mynet = enable;");
+ // Test that assignments are on separate lines.
+ verifyFormat("assign mynet = enable,\n"
+ " mynet1 = enable1;");
+ // Test that `<=` and `,` don't confuse it.
+ verifyFormat("assign mynet = enable1 <= enable2;");
+ verifyFormat("assign mynet = enable1 <= enable2,\n"
+ " mynet1 = enable3;");
+ verifyFormat("assign mynet = enable,\n"
+ " mynet1 = enable2 <= enable3;");
+ verifyFormat("assign mynet = enable(enable1, enable2);");
+}
+
TEST_F(FormatTestVerilog, BasedLiteral) {
verifyFormat("x = '0;");
verifyFormat("x = '1;");
Index: clang/lib/Format/TokenAnnotator.cpp
===================================================================
--- clang/lib/Format/TokenAnnotator.cpp
+++ clang/lib/Format/TokenAnnotator.cpp
@@ -1284,8 +1284,11 @@
Tok->setType(TT_InheritanceComma);
break;
default:
- if (Contexts.back().FirstStartOfName &&
- (Contexts.size() == 1 || startsWithInitStatement(Line))) {
+ if (Style.isVerilog() && Contexts.size() == 1 &&
+ Line.startsWith(Keywords.kw_assign)) {
+ Tok->setFinalizedType(TT_VerilogAssignComma);
+ } else if (Contexts.back().FirstStartOfName &&
+ (Contexts.size() == 1 || startsWithInitStatement(Line))) {
Contexts.back().FirstStartOfName->PartOfMultiVariableDeclStmt = true;
Line.IsMultiVariableDeclStmt = true;
}
@@ -4689,6 +4692,9 @@
return true;
}
} else if (Style.isVerilog()) {
+ // Break between assignments.
+ if (Left.is(TT_VerilogAssignComma))
+ return true;
// Break between ports of different types.
if (Left.is(TT_VerilogTypeComma))
return true;
Index: clang/lib/Format/FormatToken.h
===================================================================
--- clang/lib/Format/FormatToken.h
+++ clang/lib/Format/FormatToken.h
@@ -144,6 +144,8 @@
TYPE(UnaryOperator) \
TYPE(UnionLBrace) \
TYPE(UntouchableMacroFunc) \
+ /* Like in 'assign x = 0, y = 1;' . */ \
+ TYPE(VerilogAssignComma) \
/* like in begin : block */ \
TYPE(VerilogBlockLabelColon) \
/* The square bracket for the dimension part of the type name. \
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