eddyz87 wrote: Hi @efriedma-quic,
> That said, this isn't handling "unsigned int" correctly. "unsigned int" is > supposed to be sign-extended on RISC-V targets. (How you resolve the conflict > with PowerPC, where "unsigned int" is supposed to be zero-extended, I'm not > sure.) Could you please elaborate a bit? My understanding is that you refer to the following part of the [specification](https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf): > In RV64, 32-bit types, such as int, are stored in integer registers as proper > sign extensions of their > 32-bit values; that is, bits 63..31 are all equal. This restriction holds > even for unsigned 32-bit types. I assume that sign extension operations for RV64 take care of this detail. The way I understand this pull request -- clang would now guarantee sign or zero extension for all integral function parameters. Given that extension would be done according to the platform rules, why do you think this could be an issue? https://github.com/llvm/llvm-project/pull/84874 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
