yonghong-song wrote: @pulehui Could you check whether with -mcpu=v2 (no-alu32 mode) we have 'unsigned int' related issue or not? Specifically, given a 'unsigned int' does riscv use subregister to access 32-bit value, or use 64-bit register to access the value without zero-extension of 32-bit value?
https://github.com/llvm/llvm-project/pull/84874 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
