Author: T-Tie Date: 2024-11-08T15:01:51+08:00 New Revision: c17a914675f8fcadbf0ef440aae7e0ab6c49ec0c
URL: https://github.com/llvm/llvm-project/commit/c17a914675f8fcadbf0ef440aae7e0ab6c49ec0c DIFF: https://github.com/llvm/llvm-project/commit/c17a914675f8fcadbf0ef440aae7e0ab6c49ec0c.diff LOG: [RISCV] Add Smdbltrp and Ssdbltrp extension (#111837) Smdbltrp and Ssdbltrp supports are added in this PR. Specification link(Smdbltrp) : [https://github.com/riscv/riscv-isa-manual/blob/main/src/smdbltrp.adoc](url) Specification link(Ssdbltrp) : [https://github.com/riscv/riscv-isa-manual/blob/main/src/ssdbltrp.adoc](url) Added: Modified: clang/test/Driver/print-supported-extensions-riscv.c clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVFeatures.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 68acde65a74bfb..774dc3a4e1e756 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -120,6 +120,7 @@ // CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level) // CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level) // CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level) +// CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap Machine Level) // CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection) // CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode) // CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode) @@ -131,6 +132,7 @@ // CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering) // CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero) // CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level) +// CHECK-NEXT: ssdbltrp 1.0 'Ssdbltrp' (Double Trap Supervisor Level) // CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode) // CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking) // CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 597325ffa5e4ee..7e8d1fa2448b80 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -30,6 +30,7 @@ // CHECK-NOT: __riscv_smaia {{.*$}} // CHECK-NOT: __riscv_smcdeleg {{.*$}} // CHECK-NOT: __riscv_smcsrind {{.*$}} +// CHECK-NOT: __riscv_smdbltrp {{.*$}} // CHECK-NOT: __riscv_smepmp {{.*$}} // CHECK-NOT: __riscv_smrnmi {{.*$}} // CHECK-NOT: __riscv_smstateen {{.*$}} @@ -39,6 +40,7 @@ // CHECK-NOT: __riscv_sscofpmf {{.*$}} // CHECK-NOT: __riscv_sscounterenw {{.*$}} // CHECK-NOT: __riscv_sscsrind {{.*$}} +// CHECK-NOT: __riscv_ssdbltrp {{.*$}} // CHECK-NOT: __riscv_ssqosid{{.*$}} // CHECK-NOT: __riscv_ssstateen {{.*$}} // CHECK-NOT: __riscv_ssstrict {{.*$}} @@ -1444,6 +1446,22 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s // CHECK-SSCSRIND-EXT: __riscv_sscsrind 1000000{{$}} +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32ismdbltrp1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64ismdbltrp1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SMDBLTRP-EXT %s +// CHECK-SMDBLTRP-EXT: __riscv_smdbltrp 1000000{{$}} + +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32issdbltrp1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64issdbltrp1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSDBLTRP-EXT %s +// CHECK-SSDBLTRP-EXT: __riscv_ssdbltrp 1000000{{$}} + // RUN: %clang --target=riscv32 \ // RUN: -march=rv32i_ssqosid1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index f6f2eb45c49c17..1317221448ea5b 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -129,6 +129,7 @@ on support follow. ``Smaia`` Supported ``Smcdeleg`` Supported ``Smcsrind`` Supported + ``Smdbltrp`` Supported ``Smepmp`` Supported ``Smmpm`` Supported ``Smnpm`` Supported @@ -140,6 +141,7 @@ on support follow. ``Sscofpmf`` Assembly Support ``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__) ``Sscsrind`` Supported + ``Ssdbltrp`` Supported ``Ssnpm`` Supported ``Sspm`` Supported ``Ssqosid`` Assembly Support diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 5252ae5aadcf6a..ec57b71f82ce9c 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -186,6 +186,7 @@ Changes to the RISC-V Backend * Added `Smctr`, `Ssctr` and `Svvptc` extensions. * `-mcpu=syntacore-scr7` was added. * The `Zacas` extension is no longer marked as experimental. +* Added Smdbltrp, Ssdbltrp extensions to -march. * The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions are no longer marked as experimental. * The `Sha` extension is now supported. diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index f2e661f007d115..2d6d455a2248ea 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -936,6 +936,13 @@ def FeatureStdExtSscsrind : RISCVExtension<"sscsrind", 1, 0, "'Sscsrind' (Indirect CSR Access Supervisor Level)">; +def FeatureStdExtSmdbltrp + : RISCVExtension<"smdbltrp", 1, 0, + "'Smdbltrp' (Double Trap Machine Level)">; +def FeatureStdExtSsdbltrp + : RISCVExtension<"ssdbltrp", 1, 0, + "'Ssdbltrp' (Double Trap Supervisor Level)">; + def FeatureStdExtSmepmp : RISCVExtension<"smepmp", 1, 0, "'Smepmp' (Enhanced Physical Memory Protection)">; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index c03108c0617e75..a89ae1742bb3af 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -117,6 +117,8 @@ ; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s ; RUN: llc -mtriple=riscv32 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCSRIND %s ; RUN: llc -mtriple=riscv32 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCSRIND %s +; RUN: llc -mtriple=riscv32 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMDBLTRP %s +; RUN: llc -mtriple=riscv32 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV32SSDBLTRP %s ; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s ; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s @@ -263,6 +265,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s ; RUN: llc -mtriple=riscv64 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCSRIND %s ; RUN: llc -mtriple=riscv64 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCSRIND %s +; RUN: llc -mtriple=riscv64 -mattr=+smdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMDBLTRP %s +; RUN: llc -mtriple=riscv64 -mattr=+ssdbltrp %s -o - | FileCheck --check-prefixes=CHECK,RV64SSDBLTRP %s ; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s ; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s @@ -415,6 +419,8 @@ ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0" ; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0" ; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0" +; RV32SMDBLTRP: .attribute 5, "rv32i2p1_smdbltrp1p0" +; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0" ; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0" ; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0" ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" @@ -559,6 +565,8 @@ ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0" ; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0" ; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0" +; RV64SMDBLTRP: .attribute 5, "rv64i2p1_smdbltrp1p0" +; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0" ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0" ; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0" ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index a744a660a7076f..72a1db865e025d 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -321,6 +321,12 @@ .attribute arch, "rv32i_sscsrind1p0" # CHECK: attribute 5, "rv32i2p1_sscsrind1p0" +.attribute arch, "rv32i_smdbltrp1p0" +# CHECK: attribute 5, "rv32i2p1_smdbltrp1p0" + +.attribute arch, "rv32i_ssdbltrp1p0" +# CHECK: attribute 5, "rv32i2p1_ssdbltrp1p0" + .attribute arch, "rv32i_smcdeleg1p0" # CHECK: attribute 5, "rv32i2p1_smcdeleg1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 30f80601d96cbb..09c0f4159cc7ee 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1027,6 +1027,7 @@ R"(All available -march extensions for RISC-V smaia 1.0 smcdeleg 1.0 smcsrind 1.0 + smdbltrp 1.0 smepmp 1.0 smmpm 1.0 smnpm 1.0 @@ -1038,6 +1039,7 @@ R"(All available -march extensions for RISC-V sscofpmf 1.0 sscounterenw 1.0 sscsrind 1.0 + ssdbltrp 1.0 ssnpm 1.0 sspm 1.0 ssqosid 1.0 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
