llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang-driver Author: Jim Lin (tclin914) <details> <summary>Changes</summary> Andes A25/AX25 are 32/64bit, 5-stage pipeline, linux-capable CPUs that implement the RV[32|64]IMAFDC_Zba_Zbb_Zbc_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for A25/AX25: https://www.andestech.com/en/products-solutions/andescore-processors/riscv-a25/ https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax25/ Scheduling model will be implemented in a later PR. --- Full diff: https://github.com/llvm/llvm-project/pull/140681.diff 4 Files Affected: - (modified) clang/test/Driver/riscv-cpus.c (+36) - (modified) clang/test/Misc/target-invalid-cpu-note/riscv.c (+8-4) - (modified) llvm/docs/ReleaseNotes.md (+1) - (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+32) ``````````diff diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index dacdb03fd09d9..cebf41aa626a7 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -699,6 +699,42 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s // MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7" +// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a25 | FileCheck -check-prefix=MCPU-ANDES-A25 %s +// MCPU-ANDES-A25: "-target-cpu" "andes-a25" +// MCPU-ANDES-A25-SAME: "-target-feature" "+m" +// MCPU-ANDES-A25-SAME: "-target-feature" "+a" +// MCPU-ANDES-A25-SAME: "-target-feature" "+f" +// MCPU-ANDES-A25-SAME: "-target-feature" "+d" +// MCPU-ANDES-A25-SAME: "-target-feature" "+c" +// MCPU-ANDES-A25-SAME: "-target-feature" "+zicsr" +// MCPU-ANDES-A25-SAME: "-target-feature" "+zifencei" +// MCPU-ANDES-A25-SAME: "-target-feature" "+zba" +// MCPU-ANDES-A25-SAME: "-target-feature" "+zbb" +// MCPU-ANDES-A25-SAME: "-target-feature" "+zbc" +// MCPU-ANDES-A25-SAME: "-target-feature" "+zbs" +// MCPU-ANDES-A25-SAME: "-target-abi" "ilp32d" + +// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a25 | FileCheck -check-prefix=MTUNE-ANDES-A25 %s +// MTUNE-ANDES-A25: "-tune-cpu" "andes-a25" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax25 | FileCheck -check-prefix=MCPU-ANDES-AX25 %s +// MCPU-ANDES-AX25: "-target-cpu" "andes-ax25" +// MCPU-ANDES-AX25-SAME: "-target-feature" "+m" +// MCPU-ANDES-AX25-SAME: "-target-feature" "+a" +// MCPU-ANDES-AX25-SAME: "-target-feature" "+f" +// MCPU-ANDES-AX25-SAME: "-target-feature" "+d" +// MCPU-ANDES-AX25-SAME: "-target-feature" "+c" +// MCPU-ANDES-AX25-SAME: "-target-feature" "+zicsr" +// MCPU-ANDES-AX25-SAME: "-target-feature" "+zifencei" +// MCPU-ANDES-AX25-SAME: "-target-feature" "+zba" +// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbb" +// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbc" +// MCPU-ANDES-AX25-SAME: "-target-feature" "+zbs" +// MCPU-ANDES-AX25-SAME: "-target-abi" "lp64d" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax25 | FileCheck -check-prefix=MTUNE-ANDES-AX25 %s +// MTUNE-ANDES-AX25: "-tune-cpu" "andes-ax25" + // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s // MCPU-ANDES-N45: "-target-cpu" "andes-n45" // MCPU-ANDES-N45-SAME: "-target-feature" "+m" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index b4e83e59d296f..c57bde8aa531a 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -5,7 +5,8 @@ // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32 // RISCV32: error: unknown target CPU 'not-a-cpu' // RISCV32-NEXT: note: valid target CPU values are: -// RISCV32-SAME: {{^}} andes-a45 +// RISCV32-SAME: {{^}} andes-a25 +// RISCV32-SAME: {{^}}, andes-a45 // RISCV32-SAME: {{^}}, andes-n45 // RISCV32-SAME: {{^}}, generic-rv32 // RISCV32-SAME: {{^}}, rocket-rv32 @@ -26,7 +27,8 @@ // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' // RISCV64-NEXT: note: valid target CPU values are: -// RISCV64-SAME: {{^}} andes-ax45 +// RISCV64-SAME: {{^}} andes-ax25 +// RISCV64-SAME: {{^}}, andes-ax45 // RISCV64-SAME: {{^}}, andes-nx45 // RISCV64-SAME: {{^}}, generic-rv64 // RISCV64-SAME: {{^}}, mips-p8700 @@ -57,7 +59,8 @@ // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' // TUNE-RISCV32-NEXT: note: valid target CPU values are: -// TUNE-RISCV32-SAME: {{^}} andes-a45 +// TUNE-RISCV32-SAME: {{^}} andes-a25 +// TUNE-RISCV32-SAME: {{^}}, andes-a45 // TUNE-RISCV32-SAME: {{^}}, andes-n45 // TUNE-RISCV32-SAME: {{^}}, generic-rv32 // TUNE-RISCV32-SAME: {{^}}, rocket-rv32 @@ -82,7 +85,8 @@ // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' // TUNE-RISCV64-NEXT: note: valid target CPU values are: -// TUNE-RISCV64-SAME: {{^}} andes-ax45 +// TUNE-RISCV64-SAME: {{^}} andes-ax25 +// TUNE-RISCV64-SAME: {{^}}, andes-ax45 // TUNE-RISCV64-SAME: {{^}}, andes-nx45 // TUNE-RISCV64-SAME: {{^}}, generic-rv64 // TUNE-RISCV64-SAME: {{^}}, mips-p8700 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 9c8cc599a8daf..1ce796fc4a5a5 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -189,6 +189,7 @@ Changes to the RISC-V Backend * Adds assembler support for the Andes `XAndesvdot` (Andes Vector Dot Product extension). * Adds assembler support for the standard `Q` (Quad-Precision Floating Point) extension. +* `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index db57f5c4da24e..6d0627fa2c329 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -648,6 +648,38 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3", FeatureStdExtZcb, FeatureStdExtZcmp]>; +def ANDES_A25 : RISCVProcessorModel<"andes-a25", + NoSchedModel, + [Feature32Bit, + FeatureStdExtI, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbc, + FeatureStdExtZbs]>; + +def ANDES_AX25 : RISCVProcessorModel<"andes-ax25", + NoSchedModel, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtZicsr, + FeatureStdExtZifencei, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbc, + FeatureStdExtZbs]>; + def ANDES_N45 : RISCVProcessorModel<"andes-n45", NoSchedModel, [Feature32Bit, `````````` </details> https://github.com/llvm/llvm-project/pull/140681 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
