https://github.com/topperc updated
https://github.com/llvm/llvm-project/pull/155710
>From 41c79fa197820c96637f03c8c2f9cdcaeb3ff5cc Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.top...@sifive.com>
Date: Wed, 27 Aug 2025 15:36:08 -0700
Subject: [PATCH 1/2] [RISCV] Verify vfwmaccbf16 and vfncvtbf16 FRM argument in
SemaRISCV::CheckBuiltinFunctionCall.
We need to check that the FRM value is an integer constant
expression with value 0-4.
---
clang/lib/Sema/SemaRISCV.cpp | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index 7b16d080603bf..3ba93ff98898b 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -1000,6 +1000,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm:
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm:
case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm:
+ case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm:
return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 4);
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm:
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm:
@@ -1038,6 +1039,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tu:
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tu:
case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tu:
+ case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tu:
case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_m:
case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_m:
case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_m:
@@ -1051,6 +1053,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_m:
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_m:
case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_m:
+ case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_m:
return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 4);
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tu:
@@ -1100,6 +1103,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm:
case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tu:
@@ -1124,6 +1129,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tu:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tu:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_m:
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_m:
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_m:
@@ -1161,6 +1168,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tum:
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tum:
case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tum:
+ case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tum:
case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_tumu:
@@ -1174,6 +1182,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_tumu:
+ case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfsqrt_v_rm_mu:
case RISCVVector::BI__builtin_rvv_vfrec7_v_rm_mu:
case RISCVVector::BI__builtin_rvv_vfcvt_x_f_v_rm_mu:
@@ -1187,6 +1196,7 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfncvt_f_x_w_rm_mu:
case RISCVVector::BI__builtin_rvv_vfncvt_f_xu_w_rm_mu:
case RISCVVector::BI__builtin_rvv_vfncvt_f_f_w_rm_mu:
+ case RISCVVector::BI__builtin_rvv_vfncvtbf16_f_f_w_rm_mu:
return SemaRef.BuiltinConstantArgRange(TheCall, 3, 0, 4);
case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_m:
case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_m:
@@ -1212,6 +1222,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_m:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_m:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_m:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_m:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_m:
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tum:
@@ -1256,6 +1268,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tum:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tum:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfredosum_vs_rm_tum:
case RISCVVector::BI__builtin_rvv_vfredusum_vs_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwredosum_vs_rm_tum:
@@ -1304,6 +1318,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_tumu:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_tumu:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu:
@@ -1348,6 +1364,8 @@ bool SemaRISCV::CheckBuiltinFunctionCall(const TargetInfo
&TI,
case RISCVVector::BI__builtin_rvv_vfwmsac_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwnmsac_vf_rm_mu:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vv_rm_mu:
+ case RISCVVector::BI__builtin_rvv_vfwmaccbf16_vf_rm_mu:
return SemaRef.BuiltinConstantArgRange(TheCall, 4, 0, 4);
case RISCV::BI__builtin_riscv_ntl_load:
case RISCV::BI__builtin_riscv_ntl_store:
>From 8fea93bb7272f7c0c907bfece183456c420cd545 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.top...@sifive.com>
Date: Thu, 28 Aug 2025 21:46:21 -0700
Subject: [PATCH 2/2] fixup! add tests
---
.../vfncvtbf16-out-of-range.c | 31 +++++++++
.../vfwmaccbf16-out-of-range.c | 66 +++++++++++++++++++
2 files changed, 97 insertions(+)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfncvtbf16-out-of-range.c
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwmaccbf16-out-of-range.c
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfncvtbf16-out-of-range.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfncvtbf16-out-of-range.c
new file mode 100644
index 0000000000000..681fc91487b89
--- /dev/null
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfncvtbf16-out-of-range.c
@@ -0,0 +1,31 @@
+// requires: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN: -target-feature +v -target-feature +zvfbfmin \
+// RUN: -fsyntax-only -verify %s
+
+#include <riscv_vector.h>
+
+vbfloat16m1_t test_vfncvtbf16_f_f_w_bf16m1_rm_m(vbool16_t mask, vfloat32m2_t
src, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfncvtbf16_f_f_w_bf16m1_rm_m(mask, src, 5, vl);
+}
+
+vbfloat16m1_t test_vfncvtbf16_f_f_w_bf16m1_rm_tu(vbfloat16m1_t maskedoff,
vfloat32m2_t src, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfncvtbf16_f_f_w_bf16m1_rm_tu(maskedoff, src, 5, vl);
+}
+
+vbfloat16m1_t test_vfncvtbf16_f_f_w_bf16m1_rm_tum(vbool16_t mask,
vbfloat16m1_t maskedoff, vfloat32m2_t src, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfncvtbf16_f_f_w_bf16m1_rm_tum(mask, maskedoff, src, 5, vl);
+}
+
+vbfloat16m1_t test_vfncvtbf16_f_f_w_bf16m1_rm_tumu(vbool16_t mask,
vbfloat16m1_t maskedoff, vfloat32m2_t src, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfncvtbf16_f_f_w_bf16m1_rm_tumu(mask, maskedoff, src, 5, vl);
+}
+
+vbfloat16m1_t test_vfncvtbf16_f_f_w_bf16m1_rm_mu(vbool16_t mask, vbfloat16m1_t
maskedoff, vfloat32m2_t src, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfncvtbf16_f_f_w_bf16m1_rm_mu(mask, maskedoff, src, 5, vl);
+}
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwmaccbf16-out-of-range.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwmaccbf16-out-of-range.c
new file mode 100644
index 0000000000000..84b822d119ca7
--- /dev/null
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfwmaccbf16-out-of-range.c
@@ -0,0 +1,66 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN: -target-feature +v -target-feature +zvfbfwma \
+// RUN: -fsyntax-only -verify %s
+
+#include <riscv_vector.h>
+
+vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm(vfloat32m1_t vd, vbfloat16mf2_t vs1,
vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vv_f32m1_rm(vd, vs1, vs2, 5, vl);
+}
+
+vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm(vfloat32m1_t vd, __bf16 vs1,
vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vf_f32m1_rm(vd, vs1, vs2, 5, vl);
+}
+
+vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd,
vbfloat16mf2_t vs1, vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vv_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
+}
+
+vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd,
__bf16 vs1, vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vf_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
+}
+
+vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_tu(vfloat32m1_t vd, vbfloat16mf2_t
vs1, vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vv_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
+}
+
+vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_tu(vfloat32m1_t vd, __bf16 vs1,
vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vf_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
+}
+
+vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd,
vbfloat16mf2_t vs1, vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vv_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
+}
+
+vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd,
__bf16 vs1, vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vf_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
+}
+
+vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t
vd, vbfloat16mf2_t vs1, vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
+}
+
+vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t
vd, __bf16 vs1, vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vf_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
+}
+
+vfloat32m1_t test_vfwmaccbf16_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd,
vbfloat16mf2_t vs1, vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vv_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
+}
+
+vfloat32m1_t test_vfwmaccbf16_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd,
__bf16 vs1, vbfloat16mf2_t vs2, size_t vl) {
+ // expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
+ return __riscv_vfwmaccbf16_vf_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
+}
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