https://github.com/abhinavp5 created
https://github.com/llvm/llvm-project/pull/158142
Issue #154310
>From e5c35b529c36c7c2670e9532db7da1d7a081b6e5 Mon Sep 17 00:00:00 2001
From: abhinavp5 <abhinavpapp...@gmail.com>
Date: Wed, 20 Aug 2025 22:40:00 -0400
Subject: [PATCH 1/3] [clang] Update function attributes for F16C intrinsics to
include constexpr support
---
clang/lib/Headers/f16cintrin.h | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Headers/f16cintrin.h b/clang/lib/Headers/f16cintrin.h
index ede67afada766..cce6687dff3a0 100644
--- a/clang/lib/Headers/f16cintrin.h
+++ b/clang/lib/Headers/f16cintrin.h
@@ -19,6 +19,10 @@
__attribute__((__always_inline__, __nodebug__, __target__("f16c"),
__min_vector_width__(128)))
#define __DEFAULT_FN_ATTRS256 \
__attribute__((__always_inline__, __nodebug__, __target__("f16c"),
__min_vector_width__(256)))
+#define __DEFAULT_FN_ATTRS128_CONSTEXPR \
+ __attribute__((__always_inline__, __nodebug__, __target__("f16c"),
__min_vector_width__(128), __constexpr__))
+#define __DEFAULT_FN_ATTRS256_CONSTEXPR \
+ __attribute__((__always_inline__, __nodebug__, __target__("f16c"),
__min_vector_width__(256), __constexpr__))
/* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,
* but that's because icc can emulate these without f16c using a library call.
@@ -35,7 +39,7 @@
/// \param __a
/// A 16-bit half-precision float value.
/// \returns The converted 32-bit float value.
-static __inline float __DEFAULT_FN_ATTRS128
+static __inline float __DEFAULT_FN_ATTRS128_CONSTEXPR
_cvtsh_ss(unsigned short __a)
{
return (float)__builtin_bit_cast(__fp16, __a);
@@ -104,7 +108,7 @@ _cvtsh_ss(unsigned short __a)
/// A 128-bit vector containing 16-bit half-precision float values. The
lower
/// 64 bits are used in the conversion.
/// \returns A 128-bit vector of [4 x float] containing converted float values.
-static __inline __m128 __DEFAULT_FN_ATTRS128
+static __inline __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR
_mm_cvtph_ps(__m128i __a)
{
typedef __fp16 __v4fp16 __attribute__((__vector_size__(8)));
@@ -151,7 +155,7 @@ _mm_cvtph_ps(__m128i __a)
/// converted to 32-bit single-precision float values.
/// \returns A vector of [8 x float] containing the converted 32-bit
/// single-precision float values.
-static __inline __m256 __DEFAULT_FN_ATTRS256
+static __inline __m256 __DEFAULT_FN_ATTRS256_CONSTEXPR
_mm256_cvtph_ps(__m128i __a)
{
typedef __fp16 __v8fp16 __attribute__((__vector_size__(16),
__aligned__(16)));
>From 5bc14add67364522dffc2664fea3a8b193cb6194 Mon Sep 17 00:00:00 2001
From: abhinavp5 <abhinavpapp...@gmail.com>
Date: Thu, 11 Sep 2025 15:13:37 -0400
Subject: [PATCH 2/3] No code changes made in f16c-builtins.c
---
clang/test/CodeGen/X86/f16c-builtins.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
mode change 100644 => 100755 clang/test/CodeGen/X86/f16c-builtins.c
diff --git a/clang/test/CodeGen/X86/f16c-builtins.c
b/clang/test/CodeGen/X86/f16c-builtins.c
old mode 100644
new mode 100755
index 1bee8364f2ef8..b716a924a92dc
--- a/clang/test/CodeGen/X86/f16c-builtins.c
+++ b/clang/test/CodeGen/X86/f16c-builtins.c
@@ -5,6 +5,7 @@
#include <immintrin.h>
+#include <builtin_test_helpers.h>
float test_cvtsh_ss(unsigned short a) {
// CHECK-LABEL: test_cvtsh_ss
@@ -13,6 +14,11 @@ float test_cvtsh_ss(unsigned short a) {
return _cvtsh_ss(a);
}
+TEST_CONSTEXPR(match_float(_cvtsh_ss(0x0000), 0.0f));
+TEST_CONSTEXPR(match_float(_cvtsh_ss(0x4500), 5.0f));
+TEST_CONSTEXPR(match_float(_cvtsh_ss(0xC000), -2.0f));
+
+
unsigned short test_cvtss_sh(float a) {
// CHECK-LABEL: test_cvtss_sh
// CHECK: insertelement <4 x float> poison, float %{{.*}}, i32 0
@@ -24,6 +30,11 @@ unsigned short test_cvtss_sh(float a) {
return _cvtss_sh(a, 0);
}
+TEST_CONSTEXPR(match_v4sf(
+ _mm_cvtph_ps(_mm_setr_epi16(0x3C00, 0x4000, 0x4200, 0x4400, 0, 0, 0, 0)),
+ 1.0f, 2.0f, 3.0f, 4.0f
+));
+
__m128 test_mm_cvtph_ps(__m128i a) {
// CHECK-LABEL: test_mm_cvtph_ps
// CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <4 x i32> <i32
0, i32 1, i32 2, i32 3>
@@ -36,6 +47,10 @@ __m256 test_mm256_cvtph_ps(__m128i a) {
// CHECK: fpext <8 x half> %{{.*}} to <8 x float>
return _mm256_cvtph_ps(a);
}
+TEST_CONSTEXPR(match_v8sf(
+ _mm256_cvtph_ps(_mm_setr_epi16(0x3C00, 0x4000, 0x4200, 0x4400, 0x4500,
0x3800, 0xC000, 0x0000)),
+ 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 0.5f, -2.0f, 0.0f
+));
__m128i test_mm_cvtps_ph(__m128 a) {
// CHECK-LABEL: test_mm_cvtps_ph
>From 76542862ad258bf2c56939a13be64d2f3a6ff28c Mon Sep 17 00:00:00 2001
From: abhinavp5 <abhinavpapp...@gmail.com>
Date: Thu, 11 Sep 2025 15:34:57 -0400
Subject: [PATCH 3/3] [Headers][X86] Allow F16C f16 -> f32 intrinsics to be
used in constexpr
---
clang/lib/Headers/f16cintrin.h | 14 ++++++++++----
clang/test/CodeGen/X86/f16c-builtins.c | 16 +++++++---------
2 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/clang/lib/Headers/f16cintrin.h b/clang/lib/Headers/f16cintrin.h
index cce6687dff3a0..c3045b11775ea 100644
--- a/clang/lib/Headers/f16cintrin.h
+++ b/clang/lib/Headers/f16cintrin.h
@@ -19,10 +19,14 @@
__attribute__((__always_inline__, __nodebug__, __target__("f16c"),
__min_vector_width__(128)))
#define __DEFAULT_FN_ATTRS256 \
__attribute__((__always_inline__, __nodebug__, __target__("f16c"),
__min_vector_width__(256)))
-#define __DEFAULT_FN_ATTRS128_CONSTEXPR \
- __attribute__((__always_inline__, __nodebug__, __target__("f16c"),
__min_vector_width__(128), __constexpr__))
-#define __DEFAULT_FN_ATTRS256_CONSTEXPR \
- __attribute__((__always_inline__, __nodebug__, __target__("f16c"),
__min_vector_width__(256), __constexpr__))
+
+#ifdef __cplusplus
+#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128 constexpr
+#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256 constexpr
+#else
+#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128
+#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256
+#endif
/* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h,
* but that's because icc can emulate these without f16c using a library call.
@@ -165,5 +169,7 @@ _mm256_cvtph_ps(__m128i __a)
#undef __DEFAULT_FN_ATTRS128
#undef __DEFAULT_FN_ATTRS256
+#undef __DEFAULT_FN_ATTRS128_CONSTEXPR
+#undef __DEFAULT_FN_ATTRS256_CONSTEXPR
#endif /* __F16CINTRIN_H */
diff --git a/clang/test/CodeGen/X86/f16c-builtins.c
b/clang/test/CodeGen/X86/f16c-builtins.c
index b716a924a92dc..2ccd26272c848 100755
--- a/clang/test/CodeGen/X86/f16c-builtins.c
+++ b/clang/test/CodeGen/X86/f16c-builtins.c
@@ -5,7 +5,7 @@
#include <immintrin.h>
-#include <builtin_test_helpers.h>
+#include "builtin_test_helpers.h"
float test_cvtsh_ss(unsigned short a) {
// CHECK-LABEL: test_cvtsh_ss
@@ -14,10 +14,9 @@ float test_cvtsh_ss(unsigned short a) {
return _cvtsh_ss(a);
}
-TEST_CONSTEXPR(match_float(_cvtsh_ss(0x0000), 0.0f));
-TEST_CONSTEXPR(match_float(_cvtsh_ss(0x4500), 5.0f));
-TEST_CONSTEXPR(match_float(_cvtsh_ss(0xC000), -2.0f));
-
+TEST_CONSTEXPR(_cvtsh_ss(0x0000) == 0.0f);
+TEST_CONSTEXPR(_cvtsh_ss(0x4500) == 5.0f);
+TEST_CONSTEXPR(_cvtsh_ss(0xC000) == -2.0f);
unsigned short test_cvtss_sh(float a) {
// CHECK-LABEL: test_cvtss_sh
@@ -30,7 +29,7 @@ unsigned short test_cvtss_sh(float a) {
return _cvtss_sh(a, 0);
}
-TEST_CONSTEXPR(match_v4sf(
+TEST_CONSTEXPR(match_m128(
_mm_cvtph_ps(_mm_setr_epi16(0x3C00, 0x4000, 0x4200, 0x4400, 0, 0, 0, 0)),
1.0f, 2.0f, 3.0f, 4.0f
));
@@ -47,7 +46,7 @@ __m256 test_mm256_cvtph_ps(__m128i a) {
// CHECK: fpext <8 x half> %{{.*}} to <8 x float>
return _mm256_cvtph_ps(a);
}
-TEST_CONSTEXPR(match_v8sf(
+TEST_CONSTEXPR(match_m256(
_mm256_cvtph_ps(_mm_setr_epi16(0x3C00, 0x4000, 0x4200, 0x4400, 0x4500,
0x3800, 0xC000, 0x0000)),
1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 0.5f, -2.0f, 0.0f
));
@@ -58,8 +57,7 @@ __m128i test_mm_cvtps_ph(__m128 a) {
return _mm_cvtps_ph(a, 0);
}
-__m128i test_mm256_cvtps_ph(__m256 a) {
- // CHECK-LABEL: test_mm256_cvtps_ph
+__m128i test_mm256_cvtps_ph(__m256 a) { // CHECK-LABEL: test_mm256_cvtps_ph
// CHECK: call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %{{.*}}, i32 0)
return _mm256_cvtps_ph(a, 0);
}
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