llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Abhinav Pappu (abhinavp5) <details> <summary>Changes</summary> Issue #<!-- -->154310 --- Full diff: https://github.com/llvm/llvm-project/pull/158142.diff 2 Files Affected: - (modified) clang/lib/Headers/f16cintrin.h (+13-3) - (modified) clang/test/CodeGen/X86/f16c-builtins.c (+15-2) ``````````diff diff --git a/clang/lib/Headers/f16cintrin.h b/clang/lib/Headers/f16cintrin.h index ede67afada766..c3045b11775ea 100644 --- a/clang/lib/Headers/f16cintrin.h +++ b/clang/lib/Headers/f16cintrin.h @@ -20,6 +20,14 @@ #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, __target__("f16c"), __min_vector_width__(256))) +#ifdef __cplusplus +#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128 constexpr +#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256 constexpr +#else +#define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128 +#define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256 +#endif + /* NOTE: Intel documents the 128-bit versions of these as being in emmintrin.h, * but that's because icc can emulate these without f16c using a library call. * Since we don't do that let's leave these in f16cintrin.h. @@ -35,7 +43,7 @@ /// \param __a /// A 16-bit half-precision float value. /// \returns The converted 32-bit float value. -static __inline float __DEFAULT_FN_ATTRS128 +static __inline float __DEFAULT_FN_ATTRS128_CONSTEXPR _cvtsh_ss(unsigned short __a) { return (float)__builtin_bit_cast(__fp16, __a); @@ -104,7 +112,7 @@ _cvtsh_ss(unsigned short __a) /// A 128-bit vector containing 16-bit half-precision float values. The lower /// 64 bits are used in the conversion. /// \returns A 128-bit vector of [4 x float] containing converted float values. -static __inline __m128 __DEFAULT_FN_ATTRS128 +static __inline __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR _mm_cvtph_ps(__m128i __a) { typedef __fp16 __v4fp16 __attribute__((__vector_size__(8))); @@ -151,7 +159,7 @@ _mm_cvtph_ps(__m128i __a) /// converted to 32-bit single-precision float values. /// \returns A vector of [8 x float] containing the converted 32-bit /// single-precision float values. -static __inline __m256 __DEFAULT_FN_ATTRS256 +static __inline __m256 __DEFAULT_FN_ATTRS256_CONSTEXPR _mm256_cvtph_ps(__m128i __a) { typedef __fp16 __v8fp16 __attribute__((__vector_size__(16), __aligned__(16))); @@ -161,5 +169,7 @@ _mm256_cvtph_ps(__m128i __a) #undef __DEFAULT_FN_ATTRS128 #undef __DEFAULT_FN_ATTRS256 +#undef __DEFAULT_FN_ATTRS128_CONSTEXPR +#undef __DEFAULT_FN_ATTRS256_CONSTEXPR #endif /* __F16CINTRIN_H */ diff --git a/clang/test/CodeGen/X86/f16c-builtins.c b/clang/test/CodeGen/X86/f16c-builtins.c old mode 100644 new mode 100755 index 6a696273cb3c8..ece9cca5a6f1a --- a/clang/test/CodeGen/X86/f16c-builtins.c +++ b/clang/test/CodeGen/X86/f16c-builtins.c @@ -10,6 +10,7 @@ #include <immintrin.h> +#include "builtin_test_helpers.h" float test_cvtsh_ss(unsigned short a) { // CHECK-LABEL: test_cvtsh_ss @@ -18,6 +19,10 @@ float test_cvtsh_ss(unsigned short a) { return _cvtsh_ss(a); } +TEST_CONSTEXPR(_cvtsh_ss(0x0000) == 0.0f); +TEST_CONSTEXPR(_cvtsh_ss(0x4500) == 5.0f); +TEST_CONSTEXPR(_cvtsh_ss(0xC000) == -2.0f); + unsigned short test_cvtss_sh(float a) { // CHECK-LABEL: test_cvtss_sh // CHECK: insertelement <4 x float> poison, float %{{.*}}, i32 0 @@ -29,6 +34,11 @@ unsigned short test_cvtss_sh(float a) { return _cvtss_sh(a, 0); } +TEST_CONSTEXPR(match_m128( + _mm_cvtph_ps(_mm_setr_epi16(0x3C00, 0x4000, 0x4200, 0x4400, 0, 0, 0, 0)), + 1.0f, 2.0f, 3.0f, 4.0f +)); + __m128 test_mm_cvtph_ps(__m128i a) { // CHECK-LABEL: test_mm_cvtph_ps // CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> @@ -41,6 +51,10 @@ __m256 test_mm256_cvtph_ps(__m128i a) { // CHECK: fpext <8 x half> %{{.*}} to <8 x float> return _mm256_cvtph_ps(a); } +TEST_CONSTEXPR(match_m256( + _mm256_cvtph_ps(_mm_setr_epi16(0x3C00, 0x4000, 0x4200, 0x4400, 0x4500, 0x3800, 0xC000, 0x0000)), + 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 0.5f, -2.0f, 0.0f +)); __m128i test_mm_cvtps_ph(__m128 a) { // CHECK-LABEL: test_mm_cvtps_ph @@ -48,8 +62,7 @@ __m128i test_mm_cvtps_ph(__m128 a) { return _mm_cvtps_ph(a, 0); } -__m128i test_mm256_cvtps_ph(__m256 a) { - // CHECK-LABEL: test_mm256_cvtps_ph +__m128i test_mm256_cvtps_ph(__m256 a) { // CHECK-LABEL: test_mm256_cvtps_ph // CHECK: call <8 x i16> @llvm.x86.vcvtps2ph.256(<8 x float> %{{.*}}, i32 0) return _mm256_cvtps_ph(a, 0); } `````````` </details> https://github.com/llvm/llvm-project/pull/158142 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
