https://github.com/Ruhung created https://github.com/llvm/llvm-project/pull/159514
Add MC layer support for Andes XAndesVSIntH extension. The spec is available at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release >From 196db35807dbbc9fd692d3dd994c1a8e7bdcc190 Mon Sep 17 00:00:00 2001 From: Juhung Li <jhlee...@andestech.com> Date: Tue, 16 Sep 2025 13:36:08 +0800 Subject: [PATCH] [RISCV] Add MC layer support for Andes XAndesVSIntH extension. --- .../Driver/print-supported-extensions-riscv.c | 1 + .../riscv-target-features-andes.c | 9 +++ llvm/docs/RISCVUsage.rst | 3 + llvm/docs/ReleaseNotes.md | 1 + .../RISCV/Disassembler/RISCVDisassembler.cpp | 4 +- llvm/lib/Target/RISCV/RISCVFeatures.td | 8 +++ llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 53 ++++++++++++++++ llvm/test/CodeGen/RISCV/attributes-andes.ll | 4 ++ llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/MC/RISCV/xandesvsinth-valid.s | 60 +++++++++++++++++++ .../TargetParser/RISCVISAInfoTest.cpp | 1 + 11 files changed, 143 insertions(+), 2 deletions(-) create mode 100644 llvm/test/MC/RISCV/xandesvsinth-valid.s diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index f619d32254d15..344dda3d87612 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -165,6 +165,7 @@ // CHECK-NEXT: xandesvbfhcvt 5.0 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension) // CHECK-NEXT: xandesvdot 5.0 'XAndesVDot' (Andes Vector Dot Product Extension) // CHECK-NEXT: xandesvpackfph 5.0 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension) +// CHECK-NEXT: xandesvsinth 5.0 'XAndesVSIntH' (Andes Vector Small INT Handling Extension) // CHECK-NEXT: xandesvsintload 5.0 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension) // CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations) // CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching) diff --git a/clang/test/Preprocessor/riscv-target-features-andes.c b/clang/test/Preprocessor/riscv-target-features-andes.c index f7981bb52de6d..385d421ecb744 100644 --- a/clang/test/Preprocessor/riscv-target-features-andes.c +++ b/clang/test/Preprocessor/riscv-target-features-andes.c @@ -6,6 +6,7 @@ // CHECK-NOT: __riscv_xandesperf {{.*$}} // CHECK-NOT: __riscv_xandesbfhcvt {{.*$}} // CHECK-NOT: __riscv_xandesvbfhcvt {{.*$}} +// CHECK-NOT: __riscv_xandesvsinth {{.*$}} // CHECK-NOT: __riscv_xandesvsintload {{.*$}} // CHECK-NOT: __riscv_xandesvpackfph {{.*$}} // CHECK-NOT: __riscv_xandesvdot {{.*$}} @@ -34,6 +35,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s // CHECK-XANDESVBFHCVT: __riscv_xandesvbfhcvt 5000000{{$}} +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32i_xandesvsinth -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVSINTH %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64i_xandesvsinth -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVSINTH %s +// CHECK-XANDESVSINTH: __riscv_xandesvsinth 5000000{{$}} + // RUN: %clang --target=riscv32 \ // RUN: -march=rv32i_xandesvsintload -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVSINTLOAD %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index cfe090eddfa09..9840060f01eb6 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -526,6 +526,9 @@ The current vendor extensions supported are: ``XAndesVBFHCvt`` LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. +``XAndesVSINTH`` + LLVM implements `version 5.0.0 of the Andes Vector Small Int Handling Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. + ``XAndesVSINTLoad`` LLVM implements `version 5.0.0 of the Andes Vector INT4 Load Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 3c3799321606a..c1d9129fb8534 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -125,6 +125,7 @@ Changes to the RISC-V Backend * Ssctr and Smctr extensions are no longer experimental. * Add support for Zvfbfa (Additional BF16 vector compute support) * Adds experimental support for the 'Zibi` (Branch with Immediate) extension. +* Adds assembler support for the Andes `XAndesvsinth` (Andes Vector Small Int Handling Extension). Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index ff07122b61378..4bbaa98a524e3 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -668,8 +668,8 @@ static constexpr FeatureBitset XTHeadGroup = { RISCV::FeatureVendorXTHeadVdot}; static constexpr FeatureBitset XAndesGroup = { - RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt, - RISCV::FeatureVendorXAndesVBFHCvt, + RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt, + RISCV::FeatureVendorXAndesVBFHCvt, RISCV::FeatureVendorXAndesVSIntH, RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH, RISCV::FeatureVendorXAndesVDot}; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 95703e33926c5..d33d924d8880c 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1638,6 +1638,14 @@ def HasVendorXAndesVBFHCvt AssemblerPredicate<(all_of FeatureVendorXAndesVBFHCvt), "'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension)">; +def FeatureVendorXAndesVSIntH + : RISCVExtension<5, 0, "Andes Vector Small INT Handling Extension", + [FeatureStdExtZve32x]>; +def HasVendorXAndesVSIntH + : Predicate<"Subtarget->hasVendorXAndesVSIntH()">, + AssemblerPredicate<(all_of FeatureVendorXAndesVSIntH), + "'XAndesVSIntH' (Andes Vector Small INT Handling Extension)">; + def FeatureVendorXAndesVSIntLoad : RISCVExtension<5, 0, "Andes Vector INT4 Load Extension", [FeatureStdExtZve32x]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td index 1fb30a0b73d92..9835c033aea9c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td @@ -362,6 +362,47 @@ class NDSRVInstSDGP<bits<3> funct3, string opcodestr> let mayStore = 1; } +class NDSRVInstVSINTLN<bits<5> funct5, string opcodestr> + : RVInst<(outs VR:$vd), (ins GPRMemZeroOffset:$rs1), + opcodestr, "$vd, ${rs1}", [], InstFormatR>, + VLESchedMC { + bits<5> rs1; + bits<5> vd; + + let Inst{31-26} = 0b000001; + let Inst{25} = 1; + let Inst{24-20} = funct5; + let Inst{19-15} = rs1; + let Inst{14-12} = 0b100; + let Inst{11-7} = vd; + let Inst{6-0} = OPC_CUSTOM_2.Value; + let hasSideEffects = 0; + let mayLoad = 1; + let mayStore = 0; + let Uses = [VTYPE, VL]; +} + +class NDSRVInstVSINTCvt<bits<5> fucnt5, string opcodestr> + : RVInst<(outs VR:$vd), (ins VR:$vs, VMaskOp:$vm), + opcodestr, "$vd, $vs$vm", [], InstFormatR> { + bits<5> vs; + bits<5> vd; + bit vm; + + let Inst{31-26} = 0b000000; + let Inst{25} = vm; + let Inst{24-20} = vs; + let Inst{19-15} = fucnt5; + let Inst{14-12} = 0b100; + let Inst{11-7} = vd; + let Inst{6-0} = OPC_CUSTOM_2.Value; + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; + let Uses = [FRM, VL, VTYPE]; + let RVVConstraint = VMConstraint; +} + class NDSRVInstBFHCvt<bits<7> funct7, bits<5> rs1val, DAGOperand rdty, DAGOperand rs2ty, string opcodestr> : RVInstR<funct7, 0b100, OPC_CUSTOM_2, (outs rdty:$rd), @@ -679,6 +720,18 @@ let Uses = [FRM, VL, VTYPE] in def NDS_VFNCVT_BF16_S : NDSRVInstVBFHCvt<0b00001, "nds.vfncvt.bf16.s">; } +//===----------------------------------------------------------------------===// +// XAndesVSIntH +//===----------------------------------------------------------------------===// + +let Predicates = [HasVendorXAndesVSIntH] in { + def NDS_VFWCVT_F_N : NDSRVInstVSINTCvt<0b00100, "nds.vfwcvt.f.n.v">; + def NDS_VFWCVT_F_NU : NDSRVInstVSINTCvt<0b00101, "nds.vfwcvt.f.nu.v">; + def NDS_VFWCVT_F_B : NDSRVInstVSINTCvt<0b00110, "nds.vfwcvt.f.b.v">; + def NDS_VFWCVT_F_BU : NDSRVInstVSINTCvt<0b00111, "nds.vfwcvt.f.bu.v">; + def NDS_VLE4_V : NDSRVInstVSINTLN<0b00000, "nds.vle4.v">; +} + //===----------------------------------------------------------------------===// // XAndesVSIntLoad //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/attributes-andes.ll b/llvm/test/CodeGen/RISCV/attributes-andes.ll index ed27a9255a86f..fc2b1b123af51 100644 --- a/llvm/test/CodeGen/RISCV/attributes-andes.ll +++ b/llvm/test/CodeGen/RISCV/attributes-andes.ll @@ -3,6 +3,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV32XANDESPERF %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESBFHCVT %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESVBFHCVT %s +; RUN: llc -mtriple=riscv32 -mattr=+xandesvsinth %s -o - | FileCheck --check-prefix=RV32XANDESVSINTH %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV32XANDESVSINTLOAD %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV32XANDESVDOT %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV32XANDESVPACKFPH %s @@ -10,6 +11,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV64XANDESPERF %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESBFHCVT %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESVBFHCVT %s +; RUN: llc -mtriple=riscv64 -mattr=+xandesvsinth %s -o - | FileCheck --check-prefix=RV64XANDESVSINTH %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV64XANDESVSINTLOAD %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV64XANDESVDOT %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesvpackfph %s -o - | FileCheck --check-prefix=RV64XANDESVPACKFPH %s @@ -17,6 +19,7 @@ ; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0" ; RV32XANDESBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0" ; RV32XANDESVBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0" +; RV32XANDESVSINTH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsinth5p0" ; RV32XANDESVSINTLOAD: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0" ; RV32XANDESVDOT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0" ; RV32XANDESVPACKFPH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xandesvpackfph5p0" @@ -24,6 +27,7 @@ ; RV64XANDESPERF: .attribute 5, "rv64i2p1_xandesperf5p0" ; RV64XANDESBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0" ; RV64XANDESVBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0" +; RV64XANDESVSINTH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsinth5p0" ; RV64XANDESVSINTLOAD: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0" ; RV64XANDESVDOT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0" ; RV64XANDESVPACKFPH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xandesvpackfph5p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index a3b56c6fd3d77..2d6e44e239fad 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -190,6 +190,7 @@ ; CHECK-NEXT: xandesvbfhcvt - 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension). ; CHECK-NEXT: xandesvdot - 'XAndesVDot' (Andes Vector Dot Product Extension). ; CHECK-NEXT: xandesvpackfph - 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension). +; CHECK-NEXT: xandesvsinth - 'XAndesVSIntH' (Andes Vector Small INT Handling Extension). ; CHECK-NEXT: xandesvsintload - 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension). ; CHECK-NEXT: xcvalu - 'XCValu' (CORE-V ALU Operations). ; CHECK-NEXT: xcvbi - 'XCVbi' (CORE-V Immediate Branching). diff --git a/llvm/test/MC/RISCV/xandesvsinth-valid.s b/llvm/test/MC/RISCV/xandesvsinth-valid.s new file mode 100644 index 0000000000000..387bb116fe86f --- /dev/null +++ b/llvm/test/MC/RISCV/xandesvsinth-valid.s @@ -0,0 +1,60 @@ +# XAndesVSIntLoad - Andes Vector INT4 Load Extension +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xandesvsinth -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xandesvsinth < %s \ +# RUN: | llvm-objdump --mattr=+xandesvsinth -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc %s -triple=riscv64 -mattr=+xandesvsinth -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xandesvsinth < %s \ +# RUN: | llvm-objdump --mattr=+xandesvsinth -M no-aliases -d -r - \ +# RUN: | FileCheck -check-prefixes=CHECK-OBJ %s +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# CHECK-OBJ: nds.vfwcvt.f.n.v v8, v10 +# CHECK-ASM: nds.vfwcvt.f.n.v v8, v10 +# CHECK-ASM: encoding: [0x5b,0x44,0xa2,0x02] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}} +nds.vfwcvt.f.n.v v8, v10 +# CHECK-OBJ: nds.vfwcvt.f.n.v v8, v10, v0.t +# CHECK-ASM: nds.vfwcvt.f.n.v v8, v10, v0.t +# CHECK-ASM: encoding: [0x5b,0x44,0xa2,0x00] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}} +nds.vfwcvt.f.n.v v8, v10, v0.t +# CHECK-OBJ: nds.vfwcvt.f.nu.v v8, v10 +# CHECK-ASM: nds.vfwcvt.f.nu.v v8, v10 +# CHECK-ASM: encoding: [0x5b,0xc4,0xa2,0x02] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}} +nds.vfwcvt.f.nu.v v8, v10 +# CHECK-OBJ: nds.vfwcvt.f.nu.v v8, v10, v0.t +# CHECK-ASM: nds.vfwcvt.f.nu.v v8, v10, v0.t +# CHECK-ASM: encoding: [0x5b,0xc4,0xa2,0x00] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}} +nds.vfwcvt.f.nu.v v8, v10, v0.t +# CHECK-OBJ: nds.vfwcvt.f.b.v v8, v10 +# CHECK-ASM: nds.vfwcvt.f.b.v v8, v10 +# CHECK-ASM: encoding: [0x5b,0x44,0xa3,0x02] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}} +nds.vfwcvt.f.b.v v8, v10 +# CHECK-OBJ: nds.vfwcvt.f.b.v v8, v10, v0.t +# CHECK-ASM: nds.vfwcvt.f.b.v v8, v10, v0.t +# CHECK-ASM: encoding: [0x5b,0x44,0xa3,0x00] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}} +nds.vfwcvt.f.b.v v8, v10, v0.t +# CHECK-OBJ: nds.vfwcvt.f.bu.v v8, v10 +# CHECK-ASM: nds.vfwcvt.f.bu.v v8, v10 +# CHECK-ASM: encoding: [0x5b,0xc4,0xa3,0x02] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}} +nds.vfwcvt.f.bu.v v8, v10 +# CHECK-OBJ: nds.vfwcvt.f.bu.v v8, v10, v0.t +# CHECK-ASM: nds.vfwcvt.f.bu.v v8, v10, v0.t +# CHECK-ASM: encoding: [0x5b,0xc4,0xa3,0x00] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}} +nds.vfwcvt.f.bu.v v8, v10, v0.t +# CHECK-OBJ: nds.vle4.v v8, (a0) +# CHECK-ASM: nds.vle4.v v8, (a0) +# CHECK-ASM: encoding: [0x5b,0x44,0x05,0x06] +# CHECK-ERROR: instruction requires the following: 'XAndesVSIntH' (Andes Vector Small INT Handling Extension){{$}} +nds.vle4.v v8, (a0) diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index e953c0d11590b..2ceaa184dad67 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1137,6 +1137,7 @@ R"(All available -march extensions for RISC-V xandesvbfhcvt 5.0 xandesvdot 5.0 xandesvpackfph 5.0 + xandesvsinth 5.0 xandesvsintload 5.0 xcvalu 1.0 xcvbi 1.0 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
