https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/164820
>From 0284d120e4d54693e8ef63e53bc8a42de3a08993 Mon Sep 17 00:00:00 2001 From: Brandon Wu <[email protected]> Date: Tue, 29 Apr 2025 13:54:26 +0800 Subject: [PATCH 1/2] [RISCV] Support Zvfofp4min assembler version 0.1 OFP4 conversion extension Zvfofp4min spec: https://github.com/aswaterman/riscv-misc/blob/4404b28f3f5f5f737281624bf9da14e7649f1854/isa/zvfbfa.adoc#ofp4-conversion-extension-zvfofp4min-version-01 --- .../Driver/print-supported-extensions-riscv.c | 1 + .../test/Preprocessor/riscv-target-features.c | 8 +++++ llvm/lib/Target/RISCV/RISCVFeatures.td | 8 +++++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 3 ++ llvm/test/CodeGen/RISCV/attributes.ll | 4 +++ llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/MC/RISCV/attribute-arch.s | 3 ++ llvm/test/MC/RISCV/rvv/zvfofp4min.s | 30 +++++++++++++++++++ .../TargetParser/RISCVISAInfoTest.cpp | 1 + 9 files changed, 59 insertions(+) create mode 100644 llvm/test/MC/RISCV/rvv/zvfofp4min.s diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index cb812736786a9..07f1fc11958c2 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -224,6 +224,7 @@ // CHECK-NEXT: zalasr 0.9 'Zalasr' (Load-Acquire and Store-Release Instructions) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) +// CHECK-NEXT: zvfofp4min 0.1 'Zvfofp4min' (OFP4 conversion extension Zvfofp4min) // CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts) // CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography) // CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 77731a9776be8..b5c3f711b8ecc 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1570,6 +1570,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFA-EXT %s // CHECK-ZVFBFA-EXT: __riscv_zvfbfa 1000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zvfofp4min0p1 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFOFP4MIN-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zvfofp4min0p1 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFOFP4MIN-EXT %s +// CHECK-ZVFOFP4MIN-EXT: __riscv_zvfofp4min 1000{{$}} + // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32ifzvfofp8min0p2 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFOFP8MIN-EXT %s diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 9e6b7f0327eb8..3d88cbb4b3dbf 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -740,6 +740,14 @@ def HasStdExtZvfbfminOrZvfofp8min "'Zvfbfmin' (Vector BF16 Converts) or " "'Zvfofp8min' (Vector OFP8 Converts)">; +def FeatureStdExtZvfofp4min + : RISCVExperimentalExtension<0, 1, "OFP4 conversion extension Zvfofp4min", + [FeatureStdExtZve32f]>; +def HasStdExtZvfofp4min + : Predicate<"Subtarget->hasStdExtZvfofp4min()">, + AssemblerPredicate<(all_of FeatureStdExtZvfofp4min), + "'Zvfofp4min' (OFP4 conversion extension Zvfofp4min)">; + // Vector Cryptography and Bitmanip Extensions def FeatureStdExtZvkb diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index f46455a9acedf..037af15d15620 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -1838,5 +1838,8 @@ let Predicates = [HasVInstructionsI64, IsRV64] in { } } // Predicates = [HasVInstructionsI64, IsRV64] +let Predicates = [HasStdExtZvfofp4min] in + defm VFEXT_VF2 : VALU_MV_VS2<"vfext.vf2", 0b010010, 0b10110>; + include "RISCVInstrInfoVPseudos.td" include "RISCVInstrInfoZvfbf.td" diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 22c2d8102b5ca..aaa23057b594c 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -130,6 +130,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFA %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfofp4min %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFOFP4MIN %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfofp8min %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFOFP8MIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s @@ -280,6 +281,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFA %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfofp4min %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFOFP4MIN %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfofp8min %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFOFP8MIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s @@ -444,6 +446,7 @@ ; RV32ZVFBFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0" ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" +; RV32ZVFOFP4MIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp4min0p1_zvl32b1p0" ; RV32ZVFOFP8MIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0" ; RV32ZACAS: .attribute 5, "rv32i2p1_zaamo1p0_zacas1p0" ; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p9" @@ -592,6 +595,7 @@ ; RV64ZVFBFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0" ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" +; RV64ZVFOFP4MIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp4min0p1_zvl32b1p0" ; RV64ZVFOFP8MIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0" ; RV64ZACAS: .attribute 5, "rv64i2p1_zaamo1p0_zacas1p0" ; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p9" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 5e5f2b78e8869..ff93dad278eb1 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -57,6 +57,7 @@ ; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack). ; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements). ; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support). +; CHECK-NEXT: experimental-zvfofp4min - 'Zvfofp4min' (OFP4 conversion extension Zvfofp4min). ; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts). ; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography). ; CHECK-NEXT: experimental-zvqdotq - 'Zvqdotq' (Vector quad widening 4D Dot Product). diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 111616df254d3..e3e613620a581 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -414,6 +414,9 @@ .attribute arch, "rv32i_zvfbfwma1p0" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" +.attribute arch, "rv32i_zvfofp4min0p1" +# CHECK: attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp4min0p1_zvl32b1p0" + .attribute arch, "rv32i_zvfofp8min0p2" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0" diff --git a/llvm/test/MC/RISCV/rvv/zvfofp4min.s b/llvm/test/MC/RISCV/rvv/zvfofp4min.s new file mode 100644 index 0000000000000..c52fcdd50cef1 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvfofp4min.s @@ -0,0 +1,30 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+experimental-zvfofp4min %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfofp4min %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zvfofp4min - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfofp4min %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+experimental-zvfofp4min %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfofp4min %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zvfofp4min - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfofp4min %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +# CHECK-INST: vfext.vf2 v8, v4 +# CHECK-ENCODING: [0x57,0x24,0x4b,0x4a] +# CHECK-ERROR: instruction requires the following: 'Zvfofp4min' (OFP4 conversion extension Zvfofp4min){{$}} +# CHECK-UNKNOWN: 4a4b2457 <unknown> +vfext.vf2 v8, v4 + +# CHECK-INST: vfext.vf2 v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4b,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvfofp4min' (OFP4 conversion extension Zvfofp4min){{$}} +# CHECK-UNKNOWN: 484b2457 <unknown> +vfext.vf2 v8, v4, v0.t diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index bfc127530570d..e32eddb659cbd 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1201,6 +1201,7 @@ Experimental extensions zalasr 0.9 zvbc32e 0.7 zvfbfa 0.1 + zvfofp4min 0.1 zvfofp8min 0.2 zvkgs 0.7 zvqdotq 0.0 >From 55ee426772ffbb230151aa1c2b3657efbd96838a Mon Sep 17 00:00:00 2001 From: Brandon Wu <[email protected]> Date: Fri, 24 Oct 2025 10:28:03 -0700 Subject: [PATCH 2/2] fixup! [RISCV] Support Zvfofp4min assembler version 0.1 --- .../Driver/print-supported-extensions-riscv.c | 2 +- llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++-- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 + llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 3 --- .../Target/RISCV/RISCVInstrInfoZvfofp4min.td | 23 +++++++++++++++++++ llvm/test/CodeGen/RISCV/features-info.ll | 2 +- llvm/test/MC/RISCV/rvv/zvfofp4min.s | 4 ++-- 7 files changed, 30 insertions(+), 9 deletions(-) create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp4min.td diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 07f1fc11958c2..0f8b31b742102 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -224,7 +224,7 @@ // CHECK-NEXT: zalasr 0.9 'Zalasr' (Load-Acquire and Store-Release Instructions) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) -// CHECK-NEXT: zvfofp4min 0.1 'Zvfofp4min' (OFP4 conversion extension Zvfofp4min) +// CHECK-NEXT: zvfofp4min 0.1 'Zvfofp4min' (Vector OFP4 Converts) // CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts) // CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography) // CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 3d88cbb4b3dbf..99616aab05c86 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -741,12 +741,12 @@ def HasStdExtZvfbfminOrZvfofp8min "'Zvfofp8min' (Vector OFP8 Converts)">; def FeatureStdExtZvfofp4min - : RISCVExperimentalExtension<0, 1, "OFP4 conversion extension Zvfofp4min", + : RISCVExperimentalExtension<0, 1, "Vector OFP4 Converts", [FeatureStdExtZve32f]>; def HasStdExtZvfofp4min : Predicate<"Subtarget->hasStdExtZvfofp4min()">, AssemblerPredicate<(all_of FeatureStdExtZvfofp4min), - "'Zvfofp4min' (OFP4 conversion extension Zvfofp4min)">; + "'Zvfofp4min' (Vector OFP4 Converts)">; // Vector Cryptography and Bitmanip Extensions diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 7c89686ebfb3c..7ebc0a1a4b0d5 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2347,6 +2347,7 @@ include "RISCVInstrInfoZk.td" include "RISCVInstrInfoV.td" include "RISCVInstrInfoZvk.td" include "RISCVInstrInfoZvqdotq.td" +include "RISCVInstrInfoZvfofp4min.td" include "RISCVInstrInfoZvfofp8min.td" // Packed SIMD diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index 037af15d15620..f46455a9acedf 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -1838,8 +1838,5 @@ let Predicates = [HasVInstructionsI64, IsRV64] in { } } // Predicates = [HasVInstructionsI64, IsRV64] -let Predicates = [HasStdExtZvfofp4min] in - defm VFEXT_VF2 : VALU_MV_VS2<"vfext.vf2", 0b010010, 0b10110>; - include "RISCVInstrInfoVPseudos.td" include "RISCVInstrInfoZvfbf.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp4min.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp4min.td new file mode 100644 index 0000000000000..42cab84701783 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp4min.td @@ -0,0 +1,23 @@ +//===- RISCVInstrInfoZvfofp4min.td - 'Zvfofp4min' ----------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard 'Zvfofp4min' +// extension, providing vector conversion instructions for OFP4. +// This version is still experimental as the 'Zvfofp4min' extension hasn't been +// ratified yet. +// spec: https://github.com/aswaterman/riscv-misc/blob/4404b28f3f5f5f737281624bf9da14e7649f1854/isa/zvfbfa.adoc#ofp4-conversion-extension-zvfofp4min-version-01 +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZvfofp4min] in + defm VFEXT_VF2 : VALU_MV_VS2<"vfext.vf2", 0b010010, 0b10110>; + diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index ff93dad278eb1..fe36cd19a9dbe 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -57,7 +57,7 @@ ; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack). ; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements). ; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support). -; CHECK-NEXT: experimental-zvfofp4min - 'Zvfofp4min' (OFP4 conversion extension Zvfofp4min). +; CHECK-NEXT: experimental-zvfofp4min - 'Zvfofp4min' (Vector OFP4 Converts). ; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts). ; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography). ; CHECK-NEXT: experimental-zvqdotq - 'Zvqdotq' (Vector quad widening 4D Dot Product). diff --git a/llvm/test/MC/RISCV/rvv/zvfofp4min.s b/llvm/test/MC/RISCV/rvv/zvfofp4min.s index c52fcdd50cef1..b043cc95e3f5a 100644 --- a/llvm/test/MC/RISCV/rvv/zvfofp4min.s +++ b/llvm/test/MC/RISCV/rvv/zvfofp4min.s @@ -19,12 +19,12 @@ # CHECK-INST: vfext.vf2 v8, v4 # CHECK-ENCODING: [0x57,0x24,0x4b,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvfofp4min' (OFP4 conversion extension Zvfofp4min){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfofp4min' (Vector OFP4 Converts){{$}} # CHECK-UNKNOWN: 4a4b2457 <unknown> vfext.vf2 v8, v4 # CHECK-INST: vfext.vf2 v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4b,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvfofp4min' (OFP4 conversion extension Zvfofp4min){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfofp4min' (Vector OFP4 Converts){{$}} # CHECK-UNKNOWN: 484b2457 <unknown> vfext.vf2 v8, v4, v0.t _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
