================
@@ -227,6 +288,11 @@ mlir::LogicalResult CIRGenFunction::emitAsmStmt(const
AsmStmt &s) {
llvm::BitVector resultTypeRequiresCast;
llvm::BitVector resultRegIsFlagReg;
+ // Keep track of input constraints.
+ std::string inOutConstraints;
+ std::vector<mlir::Type> inOutArgTypes;
----------------
andykaylor wrote:
SmallVector?
https://github.com/llvm/llvm-project/pull/176239
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