================
@@ -516,17 +516,23 @@ BitVector X86RegisterInfo::getReservedRegs(const
MachineFunction &MF) const {
Reserved.set(X86::SSP);
auto &ST = MF.getSubtarget<X86Subtarget>();
- if (ST.is64Bit() && ST.hasUserReservedRegisters()) {
- // Set r# as reserved register if user required
- for (unsigned Reg = X86::R8; Reg <= X86::R15; ++Reg)
- if (ST.isRegisterReservedByUser(Reg))
- for (const MCPhysReg &SubReg : subregs_inclusive(Reg))
- Reserved.set(SubReg);
- if (ST.hasEGPR())
- for (unsigned Reg = X86::R16; Reg <= X86::R31; ++Reg)
+ if (ST.hasUserReservedRegisters()) {
----------------
efriedma-quic wrote:
I guess not directly related to your patch, but hasUserReservedRegisters() is a
non-trivial function; should we cache the result in Subtarget?
https://github.com/llvm/llvm-project/pull/186123
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