https://github.com/fileho updated 
https://github.com/llvm/llvm-project/pull/186866

From aa26cef64029a0587ed3fa632a84eef05fd92c71 Mon Sep 17 00:00:00 2001
From: Jiri Filek <[email protected]>
Date: Mon, 16 Mar 2026 20:31:56 +0100
Subject: [PATCH] [CIR][AArch64] Implement vget_lane_bf16 and vgetq_lane_bf16
 builtins

---
 clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 10 ++++++----
 .../CodeGen/AArch64/bf16-getset-intrinsics.c   | 18 ------------------
 clang/test/CodeGen/AArch64/neon/bf16-getset.c  | 16 ++++++++++++++++
 3 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp 
b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
index d9d303cd07b92..902d583698047 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp
@@ -2180,21 +2180,23 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned 
builtinID, const CallExpr *expr,
   case NEON::BI__builtin_neon_vqdmlals_lane_s32:
   case NEON::BI__builtin_neon_vqdmlals_laneq_s32:
   case NEON::BI__builtin_neon_vqdmlsls_lane_s32:
-  case NEON::BI__builtin_neon_vqdmlsls_laneq_s32:
-  case NEON::BI__builtin_neon_vget_lane_bf16:
+  case NEON::BI__builtin_neon_vqdmlsls_laneq_s32: {
     cgm.errorNYI(expr->getSourceRange(),
                  std::string("unimplemented AArch64 builtin call: ") +
                      getContext().BuiltinInfo.getName(builtinID));
     return mlir::Value{};
+  }
+  case NEON::BI__builtin_neon_vget_lane_bf16:
   case NEON::BI__builtin_neon_vduph_lane_bf16: {
     return cir::VecExtractOp::create(builder, loc, ops[0], ops[1]);
   }
-  case NEON::BI__builtin_neon_vduph_lane_f16:
-  case NEON::BI__builtin_neon_vgetq_lane_bf16:
+  case NEON::BI__builtin_neon_vduph_lane_f16: {
     cgm.errorNYI(expr->getSourceRange(),
                  std::string("unimplemented AArch64 builtin call: ") +
                      getContext().BuiltinInfo.getName(builtinID));
     return mlir::Value{};
+  }
+  case NEON::BI__builtin_neon_vgetq_lane_bf16:
   case NEON::BI__builtin_neon_vduph_laneq_bf16: {
     return cir::VecExtractOp::create(builder, loc, ops[0], ops[1]);
   }
diff --git a/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c 
b/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
index 69171902c7e69..19819d0d6c8c8 100644
--- a/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
+++ b/clang/test/CodeGen/AArch64/bf16-getset-intrinsics.c
@@ -41,24 +41,6 @@ bfloat16x4_t test_vget_low_bf16(bfloat16x8_t a) {
   return vget_low_bf16(a);
 }
 
-// CHECK-LABEL: @test_vget_lane_bf16(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[VGET_LANE:%.*]] = extractelement <4 x bfloat> [[V:%.*]], 
i32 1
-// CHECK-NEXT:    ret bfloat [[VGET_LANE]]
-//
-bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {
-  return vget_lane_bf16(v, 1);
-}
-
-// CHECK-LABEL: @test_vgetq_lane_bf16(
-// CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[VGETQ_LANE:%.*]] = extractelement <8 x bfloat> [[V:%.*]], 
i32 7
-// CHECK-NEXT:    ret bfloat [[VGETQ_LANE]]
-//
-bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
-  return vgetq_lane_bf16(v, 7);
-}
-
 // CHECK-LABEL: @test_vset_lane_bf16(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[VSET_LANE:%.*]] = insertelement <4 x bfloat> [[V:%.*]], 
bfloat [[A:%.*]], i32 1
diff --git a/clang/test/CodeGen/AArch64/neon/bf16-getset.c 
b/clang/test/CodeGen/AArch64/neon/bf16-getset.c
index eeb9209fe97a5..563110c72ba21 100644
--- a/clang/test/CodeGen/AArch64/neon/bf16-getset.c
+++ b/clang/test/CodeGen/AArch64/neon/bf16-getset.c
@@ -120,3 +120,19 @@ bfloat16x8_t test_vdupq_laneq_bf16(bfloat16x8_t v) {
     // LLVM-NEXT: ret <8 x bfloat> [[VECINIT7_I]]
     return vdupq_n_bf16(v);
   }
+
+// ALL-LABEL: @test_vget_lane_bf16(
+bfloat16_t test_vget_lane_bf16(bfloat16x4_t v) {
+  // CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !cir.bf16>
+  // LLVM: [[VGET_LANE:%.*]] = extractelement <4 x bfloat> %{{.*}}, i32 1
+  // LLVM: ret bfloat [[VGET_LANE]]
+  return vget_lane_bf16(v, 1);
+}
+
+// ALL-LABEL: @test_vgetq_lane_bf16(
+bfloat16_t test_vgetq_lane_bf16(bfloat16x8_t v) {
+  // CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !cir.bf16>
+  // LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x bfloat> %{{.*}}, i32 7
+  // LLVM: ret bfloat [[VGETQ_LANE]]
+  return vgetq_lane_bf16(v, 7);
+}

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