================
@@ -0,0 +1,65 @@
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu
-target-feature +neon -disable-O0-optnone -flax-vector-conversions=none
-emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s
--check-prefixes=LLVM
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu
-target-feature +neon -disable-O0-optnone -flax-vector-conversions=none
-fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s
--check-prefixes=LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu
-target-feature +neon -disable-O0-optnone -flax-vector-conversions=none
-fclangir -emit-cir -o - %s | FileCheck %s
--check-prefixes=CIR %}
+
+//=============================================================================
+// NOTES
+//
+// This file contains tests that were originally located in:
+// * clang/test/CodeGen/AArch64/neon-intrinsics.c
+// The main difference is the use of RUN lines that enable ClangIR lowering.
+// This file currently covers the f32/f64 wrappers that lower through
+// BI__builtin_neon_vfmaq_v.
+//
+// ACLE section headings based on v2025Q2 of the ACLE specification:
+// *
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#fused-multiply-accumulate
+//
+//=============================================================================
+
+#include <arm_neon.h>
+
+//===------------------------------------------------------===//
+// Fused multiply-accumulate, vector quad forms
----------------
banach-space wrote:
```suggestion
// 2.6.1.9.3 Fused multiply-accumulate, vector quad forms
```
https://github.com/llvm/llvm-project/pull/195602
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