================
@@ -0,0 +1,66 @@
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu
-target-feature +neon -disable-O0-optnone -flax-vector-conversions=none
-emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s
--check-prefixes=LLVM
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu
-target-feature +neon -disable-O0-optnone -flax-vector-conversions=none
-fclangir -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s
--check-prefixes=LLVM %}
+// RUN: %if cir-enabled %{%clang_cc1 -triple arm64-none-linux-gnu
-target-feature +neon -disable-O0-optnone -flax-vector-conversions=none
-fclangir -emit-cir -o - %s | FileCheck %s
--check-prefixes=CIR %}
----------------
banach-space wrote:
Could you switch to the new format?
https://github.com/llvm/llvm-project/blob/82058f949725d71b8a50cb4c691ef7ddcf21a16d/clang/test/CodeGen/AArch64/neon/intrinsics.c?plain=1#L3-L5
Thank you!
https://github.com/llvm/llvm-project/pull/195602
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