https://github.com/iamvickynguyen updated https://github.com/llvm/llvm-project/pull/196776
>From 5f1bce1208fef2f51f04b36384f063bb1eff236f Mon Sep 17 00:00:00 2001 From: Vicky Nguyen <[email protected]> Date: Mon, 4 May 2026 22:23:49 -0700 Subject: [PATCH 1/2] [CIR][AArch64] Upstream vector-shift-right-and-insert NEON builtins --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 23 +- clang/test/CodeGen/AArch64/neon-intrinsics.c | 281 --------------- clang/test/CodeGen/AArch64/neon/intrinsics.c | 339 ++++++++++++++++++ clang/test/CodeGen/AArch64/poly64.c | 28 -- 4 files changed, 361 insertions(+), 310 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 562f66d4cca16..cccd44b485bc5 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -372,6 +372,22 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( return emitNeonCall(cgf.cgm, cgf.getBuilder(), {cgf.convertType(expr->getArg(0)->getType())}, ops, llvmIntrName, cgf.convertType(expr->getType()), loc); + case NEON::BI__builtin_neon_vsrid_n_s64: + case NEON::BI__builtin_neon_vsrid_n_u64: { + CIRGenBuilderTy &B = cgf.getBuilder(); + mlir::Type scalarTy = cgf.convertType(expr->getType()); + auto v1Ty = cir::VectorType::get(scalarTy, /*size=*/1); + mlir::Value a = B.createBitcast(ops[0], v1Ty); + mlir::Value b = B.createBitcast(ops[1], v1Ty); + llvm::SmallVector<mlir::Value, 4> vsriArgs{ + a, b, B.createIntCast(ops[2], B.getUInt32Ty())}; + mlir::Value r = + emitNeonCall(cgf.cgm, B, + /*argTypes=*/{v1Ty, v1Ty, B.getUInt32Ty()}, vsriArgs, + /*intrinsicName=*/"aarch64.neon.vsri", + /*funcResTy=*/v1Ty, loc); + return B.createBitcast(r, scalarTy); + } } return nullptr; @@ -2851,7 +2867,12 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, return result; } case NEON::BI__builtin_neon_vsri_n_v: - case NEON::BI__builtin_neon_vsriq_n_v: + case NEON::BI__builtin_neon_vsriq_n_v: { + llvm::SmallVector<mlir::Value, 4> vsriArgs = { + ops[0], ops[1], builder.createIntCast(ops[2], builder.getUInt32Ty())}; + return emitNeonCall(cgm, builder, {ty, ty, builder.getUInt32Ty()}, vsriArgs, + "aarch64.neon.vsri", ty, loc); + } case NEON::BI__builtin_neon_vsli_n_v: case NEON::BI__builtin_neon_vsliq_n_v: case NEON::BI__builtin_neon_vsra_n_v: diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 424d476ad33c9..dfa4fecb1cf63 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -5329,234 +5329,6 @@ uint64x2_t test_vsraq_n_u64(uint64x2_t a, uint64x2_t b) { return vsraq_n_u64(a, b, 3); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vsri_n_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRI_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.vsri.v8i8(<8 x i8> [[A]], <8 x i8> [[B]], i32 3) -// CHECK-NEXT: ret <8 x i8> [[VSRI_N]] -// -int8x8_t test_vsri_n_s8(int8x8_t a, int8x8_t b) { - return vsri_n_s8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vsri_n_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <4 x i16> @llvm.aarch64.neon.vsri.v4i16(<4 x i16> [[VSRI_N]], <4 x i16> [[VSRI_N1]], i32 3) -// CHECK-NEXT: ret <4 x i16> [[VSRI_N2]] -// -int16x4_t test_vsri_n_s16(int16x4_t a, int16x4_t b) { - return vsri_n_s16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vsri_n_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <2 x i32> @llvm.aarch64.neon.vsri.v2i32(<2 x i32> [[VSRI_N]], <2 x i32> [[VSRI_N1]], i32 3) -// CHECK-NEXT: ret <2 x i32> [[VSRI_N2]] -// -int32x2_t test_vsri_n_s32(int32x2_t a, int32x2_t b) { - return vsri_n_s32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vsriq_n_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRI_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.vsri.v16i8(<16 x i8> [[A]], <16 x i8> [[B]], i32 3) -// CHECK-NEXT: ret <16 x i8> [[VSRI_N]] -// -int8x16_t test_vsriq_n_s8(int8x16_t a, int8x16_t b) { - return vsriq_n_s8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vsriq_n_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <8 x i16> @llvm.aarch64.neon.vsri.v8i16(<8 x i16> [[VSRI_N]], <8 x i16> [[VSRI_N1]], i32 3) -// CHECK-NEXT: ret <8 x i16> [[VSRI_N2]] -// -int16x8_t test_vsriq_n_s16(int16x8_t a, int16x8_t b) { - return vsriq_n_s16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vsriq_n_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <4 x i32> @llvm.aarch64.neon.vsri.v4i32(<4 x i32> [[VSRI_N]], <4 x i32> [[VSRI_N1]], i32 3) -// CHECK-NEXT: ret <4 x i32> [[VSRI_N2]] -// -int32x4_t test_vsriq_n_s32(int32x4_t a, int32x4_t b) { - return vsriq_n_s32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vsriq_n_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <2 x i64> @llvm.aarch64.neon.vsri.v2i64(<2 x i64> [[VSRI_N]], <2 x i64> [[VSRI_N1]], i32 3) -// CHECK-NEXT: ret <2 x i64> [[VSRI_N2]] -// -int64x2_t test_vsriq_n_s64(int64x2_t a, int64x2_t b) { - return vsriq_n_s64(a, b, 3); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vsri_n_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRI_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.vsri.v8i8(<8 x i8> [[A]], <8 x i8> [[B]], i32 3) -// CHECK-NEXT: ret <8 x i8> [[VSRI_N]] -// -uint8x8_t test_vsri_n_u8(uint8x8_t a, uint8x8_t b) { - return vsri_n_u8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vsri_n_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <4 x i16> @llvm.aarch64.neon.vsri.v4i16(<4 x i16> [[VSRI_N]], <4 x i16> [[VSRI_N1]], i32 3) -// CHECK-NEXT: ret <4 x i16> [[VSRI_N2]] -// -uint16x4_t test_vsri_n_u16(uint16x4_t a, uint16x4_t b) { - return vsri_n_u16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vsri_n_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <2 x i32> @llvm.aarch64.neon.vsri.v2i32(<2 x i32> [[VSRI_N]], <2 x i32> [[VSRI_N1]], i32 3) -// CHECK-NEXT: ret <2 x i32> [[VSRI_N2]] -// -uint32x2_t test_vsri_n_u32(uint32x2_t a, uint32x2_t b) { - return vsri_n_u32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vsriq_n_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRI_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.vsri.v16i8(<16 x i8> [[A]], <16 x i8> [[B]], i32 3) -// CHECK-NEXT: ret <16 x i8> [[VSRI_N]] -// -uint8x16_t test_vsriq_n_u8(uint8x16_t a, uint8x16_t b) { - return vsriq_n_u8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vsriq_n_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <8 x i16> @llvm.aarch64.neon.vsri.v8i16(<8 x i16> [[VSRI_N]], <8 x i16> [[VSRI_N1]], i32 3) -// CHECK-NEXT: ret <8 x i16> [[VSRI_N2]] -// -uint16x8_t test_vsriq_n_u16(uint16x8_t a, uint16x8_t b) { - return vsriq_n_u16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vsriq_n_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <4 x i32> @llvm.aarch64.neon.vsri.v4i32(<4 x i32> [[VSRI_N]], <4 x i32> [[VSRI_N1]], i32 3) -// CHECK-NEXT: ret <4 x i32> [[VSRI_N2]] -// -uint32x4_t test_vsriq_n_u32(uint32x4_t a, uint32x4_t b) { - return vsriq_n_u32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vsriq_n_u64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <2 x i64> @llvm.aarch64.neon.vsri.v2i64(<2 x i64> [[VSRI_N]], <2 x i64> [[VSRI_N1]], i32 3) -// CHECK-NEXT: ret <2 x i64> [[VSRI_N2]] -// -uint64x2_t test_vsriq_n_u64(uint64x2_t a, uint64x2_t b) { - return vsriq_n_u64(a, b, 3); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vsri_n_p8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRI_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.vsri.v8i8(<8 x i8> [[A]], <8 x i8> [[B]], i32 3) -// CHECK-NEXT: ret <8 x i8> [[VSRI_N]] -// -poly8x8_t test_vsri_n_p8(poly8x8_t a, poly8x8_t b) { - return vsri_n_p8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vsri_n_p16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <4 x i16> @llvm.aarch64.neon.vsri.v4i16(<4 x i16> [[VSRI_N]], <4 x i16> [[VSRI_N1]], i32 15) -// CHECK-NEXT: ret <4 x i16> [[VSRI_N2]] -// -poly16x4_t test_vsri_n_p16(poly16x4_t a, poly16x4_t b) { - return vsri_n_p16(a, b, 15); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vsriq_n_p8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRI_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.vsri.v16i8(<16 x i8> [[A]], <16 x i8> [[B]], i32 3) -// CHECK-NEXT: ret <16 x i8> [[VSRI_N]] -// -poly8x16_t test_vsriq_n_p8(poly8x16_t a, poly8x16_t b) { - return vsriq_n_p8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vsriq_n_p16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <8 x i16> @llvm.aarch64.neon.vsri.v8i16(<8 x i16> [[VSRI_N]], <8 x i16> [[VSRI_N1]], i32 15) -// CHECK-NEXT: ret <8 x i16> [[VSRI_N2]] -// -poly16x8_t test_vsriq_n_p16(poly16x8_t a, poly16x8_t b) { - return vsriq_n_p16(a, b, 15); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vsli_n_s8( // CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -15491,59 +15263,6 @@ uint64x1_t test_vqshlu_n_s64(int64x1_t a) { return vqshlu_n_s64(a, 1); } -// CHECK-LABEL: define dso_local i64 @test_vsrid_n_s64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRID_N_S64:%.*]] = bitcast i64 [[A]] to <1 x i64> -// CHECK-NEXT: [[VSRID_N_S641:%.*]] = bitcast i64 [[B]] to <1 x i64> -// CHECK-NEXT: [[VSRID_N_S642:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[VSRID_N_S64]], <1 x i64> [[VSRID_N_S641]], i32 63) -// CHECK-NEXT: [[VSRID_N_S643:%.*]] = bitcast <1 x i64> [[VSRID_N_S642]] to i64 -// CHECK-NEXT: ret i64 [[VSRID_N_S643]] -// -int64_t test_vsrid_n_s64(int64_t a, int64_t b) { - return (int64_t)vsrid_n_s64(a, b, 63); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vsri_n_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[VSRI_N]], <1 x i64> [[VSRI_N1]], i32 1) -// CHECK-NEXT: ret <1 x i64> [[VSRI_N2]] -// -int64x1_t test_vsri_n_s64(int64x1_t a, int64x1_t b) { - return vsri_n_s64(a, b, 1); -} - -// CHECK-LABEL: define dso_local i64 @test_vsrid_n_u64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRID_N_U64:%.*]] = bitcast i64 [[A]] to <1 x i64> -// CHECK-NEXT: [[VSRID_N_U641:%.*]] = bitcast i64 [[B]] to <1 x i64> -// CHECK-NEXT: [[VSRID_N_U642:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[VSRID_N_U64]], <1 x i64> [[VSRID_N_U641]], i32 63) -// CHECK-NEXT: [[VSRID_N_U643:%.*]] = bitcast <1 x i64> [[VSRID_N_U642]] to i64 -// CHECK-NEXT: ret i64 [[VSRID_N_U643]] -// -uint64_t test_vsrid_n_u64(uint64_t a, uint64_t b) { - return (uint64_t)vsrid_n_u64(a, b, 63); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vsri_n_u64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[VSRI_N]], <1 x i64> [[VSRI_N1]], i32 1) -// CHECK-NEXT: ret <1 x i64> [[VSRI_N2]] -// -uint64x1_t test_vsri_n_u64(uint64x1_t a, uint64x1_t b) { - return vsri_n_u64(a, b, 1); -} // CHECK-LABEL: define dso_local i64 @test_vslid_n_s64( // CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 7d3fb8fd7a3ca..41b9812c302fc 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -5265,3 +5265,342 @@ uint64_t test_vaddlvq_u32(uint32x4_t a) { // LLVM-NEXT: ret i64 [[VADDLVQ_U32_I]] return vaddlvq_u32(a); } + +//===------------------------------------------------------===// +// 2.1.3.2.9 Vector Shift Right and Insert +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-insert +//===------------------------------------------------------===// + +// LLVM-LABEL: @test_vsri_n_s8( +// CIR-LABEL: @test_vsri_n_s8( +int8x8_t test_vsri_n_s8(int8x8_t a, int8x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[VSRI_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.vsri.v8i8(<8 x i8> [[A]], <8 x i8> [[B]], i32 3) +// LLVM: ret <8 x i8> [[VSRI_N]] + return vsri_n_s8(a, b, 3); +} + +// LLVM-LABEL: @test_vsri_n_s16( +// CIR-LABEL: @test_vsri_n_s16( +int16x4_t test_vsri_n_s16(int16x4_t a, int16x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <4 x i16> @llvm.aarch64.neon.vsri.v4i16(<4 x i16> [[VSRI_N]], <4 x i16> [[VSRI_N1]], i32 3) +// LLVM: ret <4 x i16> [[VSRI_N2]] + return vsri_n_s16(a, b, 3); +} + +// LLVM-LABEL: @test_vsri_n_s32( +// CIR-LABEL: @test_vsri_n_s32( +int32x2_t test_vsri_n_s32(int32x2_t a, int32x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <2 x i32> @llvm.aarch64.neon.vsri.v2i32(<2 x i32> [[VSRI_N]], <2 x i32> [[VSRI_N1]], i32 3) +// LLVM: ret <2 x i32> [[VSRI_N2]] + return vsri_n_s32(a, b, 3); +} + +// LLVM-LABEL: @test_vsriq_n_s8( +// CIR-LABEL: @test_vsriq_n_s8( +int8x16_t test_vsriq_n_s8(int8x16_t a, int8x16_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[VSRI_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.vsri.v16i8(<16 x i8> [[A]], <16 x i8> [[B]], i32 3) +// LLVM: ret <16 x i8> [[VSRI_N]] + return vsriq_n_s8(a, b, 3); +} + +// LLVM-LABEL: @test_vsriq_n_s16( +// CIR-LABEL: @test_vsriq_n_s16( +int16x8_t test_vsriq_n_s16(int16x8_t a, int16x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <8 x i16> @llvm.aarch64.neon.vsri.v8i16(<8 x i16> [[VSRI_N]], <8 x i16> [[VSRI_N1]], i32 3) +// LLVM: ret <8 x i16> [[VSRI_N2]] + return vsriq_n_s16(a, b, 3); +} + +// LLVM-LABEL: @test_vsriq_n_s32( +// CIR-LABEL: @test_vsriq_n_s32( +int32x4_t test_vsriq_n_s32(int32x4_t a, int32x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <4 x i32> @llvm.aarch64.neon.vsri.v4i32(<4 x i32> [[VSRI_N]], <4 x i32> [[VSRI_N1]], i32 3) +// LLVM: ret <4 x i32> [[VSRI_N2]] + return vsriq_n_s32(a, b, 3); +} + +// LLVM-LABEL: @test_vsriq_n_s64( +// CIR-LABEL: @test_vsriq_n_s64( +int64x2_t test_vsriq_n_s64(int64x2_t a, int64x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <2 x i64> @llvm.aarch64.neon.vsri.v2i64(<2 x i64> [[VSRI_N]], <2 x i64> [[VSRI_N1]], i32 3) +// LLVM: ret <2 x i64> [[VSRI_N2]] + return vsriq_n_s64(a, b, 3); +} + +// LLVM-LABEL: @test_vsri_n_u8( +// CIR-LABEL: @test_vsri_n_u8( +uint8x8_t test_vsri_n_u8(uint8x8_t a, uint8x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[VSRI_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.vsri.v8i8(<8 x i8> [[A]], <8 x i8> [[B]], i32 3) +// LLVM: ret <8 x i8> [[VSRI_N]] + return vsri_n_u8(a, b, 3); +} + +// LLVM-LABEL: @test_vsri_n_u16( +// CIR-LABEL: @test_vsri_n_u16( +uint16x4_t test_vsri_n_u16(uint16x4_t a, uint16x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <4 x i16> @llvm.aarch64.neon.vsri.v4i16(<4 x i16> [[VSRI_N]], <4 x i16> [[VSRI_N1]], i32 3) +// LLVM: ret <4 x i16> [[VSRI_N2]] + return vsri_n_u16(a, b, 3); +} + +// LLVM-LABEL: @test_vsri_n_u32( +// CIR-LABEL: @test_vsri_n_u32( +uint32x2_t test_vsri_n_u32(uint32x2_t a, uint32x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <2 x i32> @llvm.aarch64.neon.vsri.v2i32(<2 x i32> [[VSRI_N]], <2 x i32> [[VSRI_N1]], i32 3) +// LLVM: ret <2 x i32> [[VSRI_N2]] + return vsri_n_u32(a, b, 3); +} + +// LLVM-LABEL: @test_vsriq_n_u8( +// CIR-LABEL: @test_vsriq_n_u8( +uint8x16_t test_vsriq_n_u8(uint8x16_t a, uint8x16_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[VSRI_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.vsri.v16i8(<16 x i8> [[A]], <16 x i8> [[B]], i32 3) +// LLVM: ret <16 x i8> [[VSRI_N]] + return vsriq_n_u8(a, b, 3); +} + +// LLVM-LABEL: @test_vsriq_n_u16( +// CIR-LABEL: @test_vsriq_n_u16( +uint16x8_t test_vsriq_n_u16(uint16x8_t a, uint16x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <8 x i16> @llvm.aarch64.neon.vsri.v8i16(<8 x i16> [[VSRI_N]], <8 x i16> [[VSRI_N1]], i32 3) +// LLVM: ret <8 x i16> [[VSRI_N2]] + return vsriq_n_u16(a, b, 3); +} + +// LLVM-LABEL: @test_vsriq_n_u32( +// CIR-LABEL: @test_vsriq_n_u32( +uint32x4_t test_vsriq_n_u32(uint32x4_t a, uint32x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <4 x i32> @llvm.aarch64.neon.vsri.v4i32(<4 x i32> [[VSRI_N]], <4 x i32> [[VSRI_N1]], i32 3) +// LLVM: ret <4 x i32> [[VSRI_N2]] + return vsriq_n_u32(a, b, 3); +} + +// LLVM-LABEL: @test_vsriq_n_u64( +// CIR-LABEL: @test_vsriq_n_u64( +uint64x2_t test_vsriq_n_u64(uint64x2_t a, uint64x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <2 x i64> @llvm.aarch64.neon.vsri.v2i64(<2 x i64> [[VSRI_N]], <2 x i64> [[VSRI_N1]], i32 3) +// LLVM: ret <2 x i64> [[VSRI_N2]] + return vsriq_n_u64(a, b, 3); +} + +// LLVM-LABEL: @test_vsri_n_p8( +// CIR-LABEL: @test_vsri_n_p8( +poly8x8_t test_vsri_n_p8(poly8x8_t a, poly8x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[VSRI_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.vsri.v8i8(<8 x i8> [[A]], <8 x i8> [[B]], i32 3) +// LLVM: ret <8 x i8> [[VSRI_N]] + return vsri_n_p8(a, b, 3); +} + +// LLVM-LABEL: @test_vsri_n_p16( +// CIR-LABEL: @test_vsri_n_p16( +poly16x4_t test_vsri_n_p16(poly16x4_t a, poly16x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <4 x i16> @llvm.aarch64.neon.vsri.v4i16(<4 x i16> [[VSRI_N]], <4 x i16> [[VSRI_N1]], i32 15) +// LLVM: ret <4 x i16> [[VSRI_N2]] + return vsri_n_p16(a, b, 15); +} + +// LLVM-LABEL: @test_vsriq_n_p8( +// CIR-LABEL: @test_vsriq_n_p8( +poly8x16_t test_vsriq_n_p8(poly8x16_t a, poly8x16_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[VSRI_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.vsri.v16i8(<16 x i8> [[A]], <16 x i8> [[B]], i32 3) +// LLVM: ret <16 x i8> [[VSRI_N]] + return vsriq_n_p8(a, b, 3); +} + +// LLVM-LABEL: @test_vsriq_n_p16( +// CIR-LABEL: @test_vsriq_n_p16( +poly16x8_t test_vsriq_n_p16(poly16x8_t a, poly16x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <8 x i16> @llvm.aarch64.neon.vsri.v8i16(<8 x i16> [[VSRI_N]], <8 x i16> [[VSRI_N1]], i32 15) +// LLVM: ret <8 x i16> [[VSRI_N2]] + return vsriq_n_p16(a, b, 15); +} + +// LLVM-LABEL: @test_vsrid_n_s64( +// CIR-LABEL: @test_vsrid_n_s64( +int64_t test_vsrid_n_s64(int64_t a, int64_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[T0:%.*]] = bitcast i64 [[A]] to <1 x i64> +// LLVM-NEXT: [[T1:%.*]] = bitcast i64 [[B]] to <1 x i64> +// LLVM-NEXT: [[T2:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[T0]], <1 x i64> [[T1]], i32 63) +// LLVM-NEXT: [[T3:%.*]] = bitcast <1 x i64> [[T2]] to i64 +// LLVM: ret i64 [[T3]] + return (int64_t)vsrid_n_s64(a, b, 63); +} + +// LLVM-LABEL: @test_vsri_n_s64( +// CIR-LABEL: @test_vsri_n_s64( +int64x1_t test_vsri_n_s64(int64x1_t a, int64x1_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[VSRI_N]], <1 x i64> [[VSRI_N1]], i32 1) +// LLVM: ret <1 x i64> [[VSRI_N2]] + return vsri_n_s64(a, b, 1); +} + +// LLVM-LABEL: @test_vsrid_n_u64( +// CIR-LABEL: @test_vsrid_n_u64( +uint64_t test_vsrid_n_u64(uint64_t a, uint64_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[T0:%.*]] = bitcast i64 [[A]] to <1 x i64> +// LLVM-NEXT: [[T1:%.*]] = bitcast i64 [[B]] to <1 x i64> +// LLVM-NEXT: [[T2:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[T0]], <1 x i64> [[T1]], i32 63) +// LLVM-NEXT: [[T3:%.*]] = bitcast <1 x i64> [[T2]] to i64 +// LLVM: ret i64 [[T3]] + return (uint64_t)vsrid_n_u64(a, b, 63); +} + +// LLVM-LABEL: @test_vsri_n_u64( +// CIR-LABEL: @test_vsri_n_u64( +uint64x1_t test_vsri_n_u64(uint64x1_t a, uint64x1_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) {{.*}} { +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[VSRI_N]], <1 x i64> [[VSRI_N1]], i32 1) +// LLVM: ret <1 x i64> [[VSRI_N2]] + return vsri_n_u64(a, b, 1); +} + +// LLVM-LABEL: @test_vsri_n_p64( +// CIR-LABEL: @test_vsri_n_p64( +poly64x1_t test_vsri_n_p64(poly64x1_t a, poly64x1_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[VSRI_N]], <1 x i64> [[VSRI_N1]], i32 33) +// LLVM: ret <1 x i64> [[VSRI_N2]] + return vsri_n_p64(a, b, 33); +} + +// LLVM-LABEL: @test_vsriq_n_p64( +// CIR-LABEL: @test_vsriq_n_p64( +poly64x2_t test_vsriq_n_p64(poly64x2_t a, poly64x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> +// LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// LLVM-NEXT: [[VSRI_N2:%.*]] = call <2 x i64> @llvm.aarch64.neon.vsri.v2i64(<2 x i64> [[VSRI_N]], <2 x i64> [[VSRI_N1]], i32 64) +// LLVM: ret <2 x i64> [[VSRI_N2]] + return vsriq_n_p64(a, b, 64); +} diff --git a/clang/test/CodeGen/AArch64/poly64.c b/clang/test/CodeGen/AArch64/poly64.c index 50617f531e6a1..7cb725490a150 100644 --- a/clang/test/CodeGen/AArch64/poly64.c +++ b/clang/test/CodeGen/AArch64/poly64.c @@ -514,31 +514,3 @@ poly64x1_t test_vext_p64(poly64x1_t a, poly64x1_t b) { poly64x2_t test_vextq_p64(poly64x2_t a, poly64x2_t b) { return vextq_p64(a, b, 1); } - -// CHECK-LABEL: define dso_local <1 x i64> @test_vsri_n_p64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsri.v1i64(<1 x i64> [[VSRI_N]], <1 x i64> [[VSRI_N1]], i32 33) -// CHECK-NEXT: ret <1 x i64> [[VSRI_N2]] -// -poly64x1_t test_vsri_n_p64(poly64x1_t a, poly64x1_t b) { - return vsri_n_p64(a, b, 33); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vsriq_n_p64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VSRI_N1:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VSRI_N2:%.*]] = call <2 x i64> @llvm.aarch64.neon.vsri.v2i64(<2 x i64> [[VSRI_N]], <2 x i64> [[VSRI_N1]], i32 64) -// CHECK-NEXT: ret <2 x i64> [[VSRI_N2]] -// -poly64x2_t test_vsriq_n_p64(poly64x2_t a, poly64x2_t b) { - return vsriq_n_p64(a, b, 64); -} >From 0e860ea3cb72ff1dfbd2b370a483c62af2ebf6f6 Mon Sep 17 00:00:00 2001 From: Vicky Nguyen <[email protected]> Date: Wed, 13 May 2026 21:16:51 -0700 Subject: [PATCH 2/2] [CIR][AArch64] Generalize NEON SISD builtin emission via TypeModifier Refactor emitCommonNeonSISDBuiltinExpr to derive argument and result types from TypeModifier flags, mirroring the ARM.cpp flow in EmitCommonNeonSISDBuiltinExpr + LookupNeonLLVMIntrinsic. This keeps SISD lowering in one generic path and removes builtin-specific type-shaping logic. And edit comments and test labels. --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 95 +++++++++++++++---- clang/test/CodeGen/AArch64/neon/intrinsics.c | 76 +++++---------- 2 files changed, 102 insertions(+), 69 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index cccd44b485bc5..5bad95f11276a 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -257,6 +257,68 @@ static cir::VectorType getNeonPairwiseWidenInputType(cir::VectorType resType, return result; } +// Derive the LLVM intrinsic's per-operand argument types and its result +// type for use when emitting the intrinsic call. +// +// `modifier` is the TypeModifier bitmask from `ARMVectorIntrinsicInfo` +// (callers pass `info.TypeModifier`; see AArch64CodeGenUtils.h). It encodes +// how the intrinsic's argument and return types relate to the builtin's +// scalar types. For SISD builtins the key flags are: +// - VectorizeArgTypes: wrap each arg type into a fixed-width vector +// - Use64BitVectors / Use128BitVectors: choose the vector width +// (when neither is set the vector has 1 element) +// - AddRetType / VectorizeRetType: analogous flags for the return type +// +// ARM.cpp lets LLVM resolve the intrinsic's signature (via +// `CGM.getIntrinsic`) and then walks the resolved Function* formal +// parameter types. CIR has no LLVMContext here, so we derive the same +// argument/result types directly from the Clang operand types. +static std::pair<mlir::Type, llvm::SmallVector<mlir::Type>> +deriveNeonSISDIntrinsicOperandTypes(CIRGenFunction &cgf, unsigned modifier, + mlir::Type arg0Ty, mlir::Type resultTy, + llvm::ArrayRef<mlir::Value> ops) { + int vectorSize = 0; + if (modifier & Use64BitVectors) + vectorSize = 64; + else if (modifier & Use128BitVectors) + vectorSize = 128; + + auto wrapAsVector = [&](mlir::Type ty) -> cir::VectorType { + unsigned bits = cgf.cgm.getDataLayout().getTypeSizeInBits(ty); + unsigned elts = vectorSize ? vectorSize / bits : 1; + return cir::VectorType::get(ty, elts); + }; + + // Determine the vectorized data type. + cir::VectorType vecArgTy; + if (modifier & VectorizeArgTypes) + vecArgTy = wrapAsVector(arg0Ty); + + // Determine the intrinsic result type: `VectorizeRetType` returns a + // vector; otherwise, if data args are vectorized and `AddRetType` is + // unset, use a vector return with the same shape as those args. + mlir::Type funcResTy = resultTy; + if (modifier & VectorizeRetType) + funcResTy = wrapAsVector(resultTy); + else if (vecArgTy && !(modifier & AddRetType)) + funcResTy = wrapAsVector(resultTy); + + // When VectorizeArgTypes is set, wrap every operand that has the same + // scalar type as arg0 into a vector. This covers intrinsics with multiple + // data operands of the same type (e.g. vsri takes two data operands, + // both of which must be wrapped into the same vector type). + llvm::SmallVector<mlir::Type> argTypes; + argTypes.reserve(ops.size()); + for (mlir::Value op : ops) { + if ((modifier & VectorizeArgTypes) && vecArgTy && op.getType() == arg0Ty) + argTypes.push_back(vecArgTy); + else + argTypes.push_back(op.getType()); + } + + return {funcResTy, std::move(argTypes)}; +} + static mlir::Value emitCommonNeonSISDBuiltinExpr( CIRGenFunction &cgf, const ARMVectorIntrinsicInfo &info, llvm::SmallVectorImpl<mlir::Value> &ops, const CallExpr *expr) { @@ -369,28 +431,23 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( case NEON::BI__builtin_neon_vmaxv_f32: case NEON::BI__builtin_neon_vmaxvq_f32: case NEON::BI__builtin_neon_vmaxvq_f64: - return emitNeonCall(cgf.cgm, cgf.getBuilder(), - {cgf.convertType(expr->getArg(0)->getType())}, ops, - llvmIntrName, cgf.convertType(expr->getType()), loc); case NEON::BI__builtin_neon_vsrid_n_s64: - case NEON::BI__builtin_neon_vsrid_n_u64: { - CIRGenBuilderTy &B = cgf.getBuilder(); - mlir::Type scalarTy = cgf.convertType(expr->getType()); - auto v1Ty = cir::VectorType::get(scalarTy, /*size=*/1); - mlir::Value a = B.createBitcast(ops[0], v1Ty); - mlir::Value b = B.createBitcast(ops[1], v1Ty); - llvm::SmallVector<mlir::Value, 4> vsriArgs{ - a, b, B.createIntCast(ops[2], B.getUInt32Ty())}; - mlir::Value r = - emitNeonCall(cgf.cgm, B, - /*argTypes=*/{v1Ty, v1Ty, B.getUInt32Ty()}, vsriArgs, - /*intrinsicName=*/"aarch64.neon.vsri", - /*funcResTy=*/v1Ty, loc); - return B.createBitcast(r, scalarTy); - } + case NEON::BI__builtin_neon_vsrid_n_u64: + break; } - return nullptr; + CIRGenBuilderTy &builder = cgf.getBuilder(); + mlir::Type arg0Ty = cgf.convertType(expr->getArg(0)->getType()); + mlir::Type resultTy = cgf.convertType(expr->getType()); + + // Derive per-operand argument types and the result type from the + // TypeModifier flags. `emitNeonCall` takes care of per-operand + // bitcasts to `argTypes`. + auto [funcResTy, argTypes] = deriveNeonSISDIntrinsicOperandTypes( + cgf, info.TypeModifier, arg0Ty, resultTy, ops); + + return emitNeonCall(cgf.cgm, builder, std::move(argTypes), ops, llvmIntrName, + funcResTy, loc); } //===----------------------------------------------------------------------===// diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 41b9812c302fc..743103b343f08 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -5271,8 +5271,7 @@ uint64_t test_vaddlvq_u32(uint32x4_t a) { // https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-insert //===------------------------------------------------------===// -// LLVM-LABEL: @test_vsri_n_s8( -// CIR-LABEL: @test_vsri_n_s8( +// ALL-LABEL: @test_vsri_n_s8( int8x8_t test_vsri_n_s8(int8x8_t a, int8x8_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5282,8 +5281,7 @@ int8x8_t test_vsri_n_s8(int8x8_t a, int8x8_t b) { return vsri_n_s8(a, b, 3); } -// LLVM-LABEL: @test_vsri_n_s16( -// CIR-LABEL: @test_vsri_n_s16( +// ALL-LABEL: @test_vsri_n_s16( int16x4_t test_vsri_n_s16(int16x4_t a, int16x4_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5297,8 +5295,7 @@ int16x4_t test_vsri_n_s16(int16x4_t a, int16x4_t b) { return vsri_n_s16(a, b, 3); } -// LLVM-LABEL: @test_vsri_n_s32( -// CIR-LABEL: @test_vsri_n_s32( +// ALL-LABEL: @test_vsri_n_s32( int32x2_t test_vsri_n_s32(int32x2_t a, int32x2_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5312,8 +5309,7 @@ int32x2_t test_vsri_n_s32(int32x2_t a, int32x2_t b) { return vsri_n_s32(a, b, 3); } -// LLVM-LABEL: @test_vsriq_n_s8( -// CIR-LABEL: @test_vsriq_n_s8( +// ALL-LABEL: @test_vsriq_n_s8( int8x16_t test_vsriq_n_s8(int8x16_t a, int8x16_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5323,8 +5319,7 @@ int8x16_t test_vsriq_n_s8(int8x16_t a, int8x16_t b) { return vsriq_n_s8(a, b, 3); } -// LLVM-LABEL: @test_vsriq_n_s16( -// CIR-LABEL: @test_vsriq_n_s16( +// ALL-LABEL: @test_vsriq_n_s16( int16x8_t test_vsriq_n_s16(int16x8_t a, int16x8_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5338,8 +5333,7 @@ int16x8_t test_vsriq_n_s16(int16x8_t a, int16x8_t b) { return vsriq_n_s16(a, b, 3); } -// LLVM-LABEL: @test_vsriq_n_s32( -// CIR-LABEL: @test_vsriq_n_s32( +// ALL-LABEL: @test_vsriq_n_s32( int32x4_t test_vsriq_n_s32(int32x4_t a, int32x4_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5353,8 +5347,7 @@ int32x4_t test_vsriq_n_s32(int32x4_t a, int32x4_t b) { return vsriq_n_s32(a, b, 3); } -// LLVM-LABEL: @test_vsriq_n_s64( -// CIR-LABEL: @test_vsriq_n_s64( +// ALL-LABEL: @test_vsriq_n_s64( int64x2_t test_vsriq_n_s64(int64x2_t a, int64x2_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5368,8 +5361,7 @@ int64x2_t test_vsriq_n_s64(int64x2_t a, int64x2_t b) { return vsriq_n_s64(a, b, 3); } -// LLVM-LABEL: @test_vsri_n_u8( -// CIR-LABEL: @test_vsri_n_u8( +// ALL-LABEL: @test_vsri_n_u8( uint8x8_t test_vsri_n_u8(uint8x8_t a, uint8x8_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5379,8 +5371,7 @@ uint8x8_t test_vsri_n_u8(uint8x8_t a, uint8x8_t b) { return vsri_n_u8(a, b, 3); } -// LLVM-LABEL: @test_vsri_n_u16( -// CIR-LABEL: @test_vsri_n_u16( +// ALL-LABEL: @test_vsri_n_u16( uint16x4_t test_vsri_n_u16(uint16x4_t a, uint16x4_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5394,8 +5385,7 @@ uint16x4_t test_vsri_n_u16(uint16x4_t a, uint16x4_t b) { return vsri_n_u16(a, b, 3); } -// LLVM-LABEL: @test_vsri_n_u32( -// CIR-LABEL: @test_vsri_n_u32( +// ALL-LABEL: @test_vsri_n_u32( uint32x2_t test_vsri_n_u32(uint32x2_t a, uint32x2_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5409,8 +5399,7 @@ uint32x2_t test_vsri_n_u32(uint32x2_t a, uint32x2_t b) { return vsri_n_u32(a, b, 3); } -// LLVM-LABEL: @test_vsriq_n_u8( -// CIR-LABEL: @test_vsriq_n_u8( +// ALL-LABEL: @test_vsriq_n_u8( uint8x16_t test_vsriq_n_u8(uint8x16_t a, uint8x16_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5420,8 +5409,7 @@ uint8x16_t test_vsriq_n_u8(uint8x16_t a, uint8x16_t b) { return vsriq_n_u8(a, b, 3); } -// LLVM-LABEL: @test_vsriq_n_u16( -// CIR-LABEL: @test_vsriq_n_u16( +// ALL-LABEL: @test_vsriq_n_u16( uint16x8_t test_vsriq_n_u16(uint16x8_t a, uint16x8_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5435,8 +5423,7 @@ uint16x8_t test_vsriq_n_u16(uint16x8_t a, uint16x8_t b) { return vsriq_n_u16(a, b, 3); } -// LLVM-LABEL: @test_vsriq_n_u32( -// CIR-LABEL: @test_vsriq_n_u32( +// ALL-LABEL: @test_vsriq_n_u32( uint32x4_t test_vsriq_n_u32(uint32x4_t a, uint32x4_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5450,8 +5437,7 @@ uint32x4_t test_vsriq_n_u32(uint32x4_t a, uint32x4_t b) { return vsriq_n_u32(a, b, 3); } -// LLVM-LABEL: @test_vsriq_n_u64( -// CIR-LABEL: @test_vsriq_n_u64( +// ALL-LABEL: @test_vsriq_n_u64( uint64x2_t test_vsriq_n_u64(uint64x2_t a, uint64x2_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5465,8 +5451,7 @@ uint64x2_t test_vsriq_n_u64(uint64x2_t a, uint64x2_t b) { return vsriq_n_u64(a, b, 3); } -// LLVM-LABEL: @test_vsri_n_p8( -// CIR-LABEL: @test_vsri_n_p8( +// ALL-LABEL: @test_vsri_n_p8( poly8x8_t test_vsri_n_p8(poly8x8_t a, poly8x8_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5476,8 +5461,7 @@ poly8x8_t test_vsri_n_p8(poly8x8_t a, poly8x8_t b) { return vsri_n_p8(a, b, 3); } -// LLVM-LABEL: @test_vsri_n_p16( -// CIR-LABEL: @test_vsri_n_p16( +// ALL-LABEL: @test_vsri_n_p16( poly16x4_t test_vsri_n_p16(poly16x4_t a, poly16x4_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5491,8 +5475,7 @@ poly16x4_t test_vsri_n_p16(poly16x4_t a, poly16x4_t b) { return vsri_n_p16(a, b, 15); } -// LLVM-LABEL: @test_vsriq_n_p8( -// CIR-LABEL: @test_vsriq_n_p8( +// ALL-LABEL: @test_vsriq_n_p8( poly8x16_t test_vsriq_n_p8(poly8x16_t a, poly8x16_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5502,8 +5485,7 @@ poly8x16_t test_vsriq_n_p8(poly8x16_t a, poly8x16_t b) { return vsriq_n_p8(a, b, 3); } -// LLVM-LABEL: @test_vsriq_n_p16( -// CIR-LABEL: @test_vsriq_n_p16( +// ALL-LABEL: @test_vsriq_n_p16( poly16x8_t test_vsriq_n_p16(poly16x8_t a, poly16x8_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5517,8 +5499,7 @@ poly16x8_t test_vsriq_n_p16(poly16x8_t a, poly16x8_t b) { return vsriq_n_p16(a, b, 15); } -// LLVM-LABEL: @test_vsrid_n_s64( -// CIR-LABEL: @test_vsrid_n_s64( +// ALL-LABEL: @test_vsrid_n_s64( int64_t test_vsrid_n_s64(int64_t a, int64_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5531,8 +5512,7 @@ int64_t test_vsrid_n_s64(int64_t a, int64_t b) { return (int64_t)vsrid_n_s64(a, b, 63); } -// LLVM-LABEL: @test_vsri_n_s64( -// CIR-LABEL: @test_vsri_n_s64( +// ALL-LABEL: @test_vsri_n_s64( int64x1_t test_vsri_n_s64(int64x1_t a, int64x1_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5546,8 +5526,7 @@ int64x1_t test_vsri_n_s64(int64x1_t a, int64x1_t b) { return vsri_n_s64(a, b, 1); } -// LLVM-LABEL: @test_vsrid_n_u64( -// CIR-LABEL: @test_vsrid_n_u64( +// ALL-LABEL: @test_vsrid_n_u64( uint64_t test_vsrid_n_u64(uint64_t a, uint64_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5560,8 +5539,7 @@ uint64_t test_vsrid_n_u64(uint64_t a, uint64_t b) { return (uint64_t)vsrid_n_u64(a, b, 63); } -// LLVM-LABEL: @test_vsri_n_u64( -// CIR-LABEL: @test_vsri_n_u64( +// ALL-LABEL: @test_vsri_n_u64( uint64x1_t test_vsri_n_u64(uint64x1_t a, uint64x1_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" @@ -5575,12 +5553,11 @@ uint64x1_t test_vsri_n_u64(uint64x1_t a, uint64x1_t b) { return vsri_n_u64(a, b, 1); } -// LLVM-LABEL: @test_vsri_n_p64( -// CIR-LABEL: @test_vsri_n_p64( +// ALL-LABEL: @test_vsri_n_p64( poly64x1_t test_vsri_n_p64(poly64x1_t a, poly64x1_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" -// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> // LLVM-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> // LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> @@ -5590,12 +5567,11 @@ poly64x1_t test_vsri_n_p64(poly64x1_t a, poly64x1_t b) { return vsri_n_p64(a, b, 33); } -// LLVM-LABEL: @test_vsriq_n_p64( -// CIR-LABEL: @test_vsriq_n_p64( +// ALL-LABEL: @test_vsriq_n_p64( poly64x2_t test_vsriq_n_p64(poly64x2_t a, poly64x2_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.vsri" -// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) {{.*}} { // LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> // LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> // LLVM-NEXT: [[VSRI_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
