================
@@ -2265,32 +2268,54 @@ void
AArch64DAGToDAGISel::SelectMultiVectorLutiLane(SDNode *Node,
CurDAG->RemoveDeadNode(Node);
}
+void AArch64DAGToDAGISel::SelectMultiVectorLuti6LaneX4(SDNode *Node,
+ unsigned Opc,
+ unsigned NumIndexVecs) {
+ unsigned ImmOp = 3 + NumIndexVecs;
+ auto *Imm = dyn_cast<ConstantSDNode>(Node->getOperand(ImmOp));
+ if (Imm && Imm->getZExtValue() > 1)
+ return;
+
+ SmallVector<SDValue, 3> IndexRegs(Node->ops().slice(3, NumIndexVecs));
+ SDValue Ops[] = {createZTuple({Node->getOperand(1), Node->getOperand(2)}),
+ createZTuple(IndexRegs), Node->getOperand(ImmOp)};
+
+ SDLoc DL(Node);
+ EVT VT = Node->getValueType(0);
+ SDNode *Instruction = CurDAG->getMachineNode(Opc, DL, MVT::Untyped, Ops);
+ SDValue SuperReg(Instruction, 0);
+
+ for (unsigned I = 0; I < 4; ++I)
+ ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(
+ AArch64::zsub0 + I, DL, VT, SuperReg));
+
+ CurDAG->RemoveDeadNode(Node);
+}
+
void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
unsigned NumOutVecs,
- unsigned Opc) {
+ unsigned Opc,
+ unsigned NumInVecs) {
SDValue ZtValue;
if (!ImmToReg<AArch64::ZT0, 0>(Node->getOperand(2), ZtValue))
return;
- SDValue Chain = Node->getOperand(0);
- SDValue Ops[] = {ZtValue,
- createZMulTuple({Node->getOperand(3), Node->getOperand(4)}),
- Chain};
+ SmallVector<SDValue, 4> Regs(Node->ops().slice(3, NumInVecs));
+ SDValue ZTuple = NumInVecs == 3 ? createZTuple(Regs) : createZMulTuple(Regs);
+ SDValue Ops[] = {ZtValue, ZTuple, Node->getOperand(0)};
SDLoc DL(Node);
EVT VT = Node->getValueType(0);
SDNode *Instruction =
CurDAG->getMachineNode(Opc, DL, {MVT::Untyped, MVT::Other}, Ops);
- SDValue SuperReg = SDValue(Instruction, 0);
+ SDValue SuperReg(Instruction, 0);
----------------
CarolineConcatto wrote:
Unwanted change?
https://github.com/llvm/llvm-project/pull/187046
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