================
@@ -3978,14 +3983,21 @@ class sme2_luti6_vector_vg4_base<RegisterOperand zd_ty,
string asm>
}
class sme2_luti6_vector_vg4_consecutive<string asm>
- : sme2_luti6_vector_vg4_base<ZZZZ_h_mul_r, asm> {
+ : sme2_luti6_vector_vg4_base<ZZZZ_h_mul_r, ZZ_Any, asm> {
+ let Inst{15-10} = 0b111101;
+ let Inst{4-2} = Zd;
+ let Inst{1-0} = 0b00;
+}
+
+class sme2_luti6_vector_vg4_consecutive_x3<string asm>
----------------
jthackray wrote:
This has been refactored away; see your later comment about "try to understand
how aarch64_sme_luti6_lane_x4_x3 maps to LUTI6_4Z2Z2ZI"
https://github.com/llvm/llvm-project/pull/187046
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