llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: LiqinWeng (LiqinWeng) <details> <summary>Changes</summary> SPEC: https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md --- Patch is 38.01 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/202533.diff 18 Files Affected: - (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1) - (modified) clang/test/Driver/riscv-cpus.c (+1) - (modified) llvm/docs/RISCVUsage.rst (+4) - (modified) llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp (+80-1) - (modified) llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp (+31-1) - (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h (+62) - (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp (+10) - (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h (+2) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+8) - (modified) llvm/lib/Target/RISCV/RISCVInstrFormats.td (+1) - (modified) llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td (+199-3) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+6) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td (+62) - (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+2-1) - (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.td (+4) - (modified) llvm/test/CodeGen/RISCV/features-info.ll (+1) - (modified) llvm/test/MC/RISCV/xsmtvdot-valid.s (+16-16) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1) ``````````diff diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 29731e565ecfc..3ea2b846ee5d5 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -228,6 +228,7 @@ // CHECK-NEXT: xsifivecdiscarddlone 1.0 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction) // CHECK-NEXT: xsifivecflushdlone 1.0 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction) // CHECK-NEXT: xsmtvdot 1.0 'XSMTVDot' (SpacemiT Vector Dot Product Extension) +// CHECK-NEXT: xsmtvdotii 1.0 'XSMTVDotII' (SpacemiT Vector Dot Product 2.0 Extension) // CHECK-NEXT: xtheadba 1.0 'XTHeadBa' (T-Head address calculation instructions) // CHECK-NEXT: xtheadbb 1.0 'XTHeadBb' (T-Head basic bit-manipulation instructions) // CHECK-NEXT: xtheadbs 1.0 'XTHeadBs' (T-Head single-bit instructions) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 99a4c0601b41b..dffdf8dbda9a6 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -106,6 +106,7 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-a100 | FileCheck -check-prefix=MCPU-SPACEMIT-A100 %s // MCPU-SPACEMIT-A100: "-target-cpu" "spacemit-a100" // COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-spacemit-a100.c` +// MCPU-SPACEMIT-A100-SAME: "-target-feature" "+xsmtvdotii" // MCPU-SPACEMIT-A100-SAME: "-target-abi" "lp64d" // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=spacemit-a100 | FileCheck -check-prefix=MTUNE-SPACEMIT-A100 %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 166b5dd6352db..8d1ab1fa914b3 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -575,6 +575,10 @@ The current vendor extensions supported are: SpacemiT defines `Integrated Matrix Extension (IME) specification <https://github.com/spacemit-com/riscv-ime-extension-spec/releases/tag/v1.0>`__. LLVM implement the hardware-adapted subset for SpacemiT X60, defined in the `feature document <https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1>`__ by SpacemiT. All instructions are prefixed with `smt.` as described in the implementation guide. Note that this implemented subset is `version 1.0.0 of the SpacemiT Vector Dot Product Extension specification`, which is strictly a subset of the full IME specification to reflect the capabilities of SpacemiT X60 hardware correctly. +``XSMTVDotII`` + SpacemiT defines `https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md`. + LLVM implement the hardware-adapted subset for SpacemiT A100 + Experimental C Intrinsics ========================= diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 93fb1fa5a889f..5b603b7bb4482 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -215,6 +215,7 @@ class RISCVAsmParser : public MCTargetAsmParser { template <bool IsRV64Inst> ParseStatus parseGPRPair(OperandVector &Operands); ParseStatus parseGPRPair(OperandVector &Operands, bool IsRV64Inst); ParseStatus parseFRMArg(OperandVector &Operands); + ParseStatus parseSMTVType(OperandVector &Operands); ParseStatus parseFenceArg(OperandVector &Operands); ParseStatus parseRegList(OperandVector &Operands, bool MustIncludeS0 = false); ParseStatus parseRegListS0(OperandVector &Operands) { @@ -289,6 +290,7 @@ class RISCVAsmParser : public MCTargetAsmParser { std::unique_ptr<RISCVOperand> defaultMaskRegOp() const; std::unique_ptr<RISCVOperand> defaultFRMArgOp() const; std::unique_ptr<RISCVOperand> defaultFRMArgLegacyOp() const; + std::unique_ptr<RISCVOperand> defaultSMTVType(); public: enum RISCVMatchResultTy : unsigned { @@ -348,6 +350,7 @@ struct RISCVOperand final : public MCParsedAsmOperand { FPImmediate, SystemRegister, VType, + SMTVType, FRM, Fence, RegList, @@ -381,6 +384,10 @@ struct RISCVOperand final : public MCParsedAsmOperand { unsigned Val; }; + struct SMTVTypeOp { + XSMTVTypeMode::SMTVTypeMode SMTVType; + }; + struct FRMOp { RISCVFPRndMode::RoundingMode FRM; }; @@ -410,6 +417,7 @@ struct RISCVOperand final : public MCParsedAsmOperand { FPImmOp FPImm; SysRegOp SysReg; VTypeOp VType; + SMTVTypeOp SMTVType; FRMOp FRM; FenceOp Fence; RegListOp RegList; @@ -443,6 +451,9 @@ struct RISCVOperand final : public MCParsedAsmOperand { case KindTy::VType: VType = o.VType; break; + case KindTy::SMTVType: + SMTVType = o.SMTVType; + break; case KindTy::FRM: FRM = o.FRM; break; @@ -653,6 +664,22 @@ struct RISCVOperand final : public MCParsedAsmOperand { bool isFRMArgLegacy() const { return Kind == KindTy::FRM; } bool isRTZArg() const { return isFRMArg() && FRM.FRM == RISCVFPRndMode::RTZ; } + // Return true if the operand is a SpacemiT AI Inst support i4/i8 + bool isSMTVType0() const { + return Kind == KindTy::SMTVType && + XSMTVTypeMode::isValidSMTVTypeInt(SMTVType.SMTVType); + } + + // Return true if the operand is a SpacemiT AI Inst support bfp16/fp16 + bool isSMTVType1() const { + return Kind == KindTy::SMTVType && + XSMTVTypeMode::isValidSMTVTypeFP(SMTVType.SMTVType); + } + + bool isSMTI8() const { + return isSMTVType0() && SMTVType.SMTVType == XSMTVTypeMode::SMT_I8; + } + /// Return true if the operand is a valid fli.s floating-point immediate. bool isLoadFPImm() const { if (isExpr()) @@ -1069,6 +1096,11 @@ struct RISCVOperand final : public MCParsedAsmOperand { return Fence.Val; } + XSMTVTypeMode::SMTVTypeMode getSMTVType() const { + assert(Kind == KindTy::SMTVType && "Invalid type access!"); + return SMTVType.SMTVType; + } + void print(raw_ostream &OS, const MCAsmInfo &MAI) const override { auto RegName = [](MCRegister Reg) { if (Reg) @@ -1106,6 +1138,11 @@ struct RISCVOperand final : public MCParsedAsmOperand { OS << roundingModeToString(getFRM()); OS << '>'; break; + case KindTy::SMTVType: + OS << "<smt: "; + SMTVTypeModeToString(getSMTVType()); + OS << '>'; + break; case KindTy::Fence: OS << "<fence: "; OS << getFence(); @@ -1184,6 +1221,15 @@ struct RISCVOperand final : public MCParsedAsmOperand { return Op; } + static std::unique_ptr<RISCVOperand> + createSMTVType(XSMTVTypeMode::SMTVTypeMode VType, SMLoc S) { + auto Op = std::make_unique<RISCVOperand>(KindTy::SMTVType); + Op->SMTVType.SMTVType = VType; + Op->StartLoc = S; + Op->EndLoc = S; + return Op; + } + static std::unique_ptr<RISCVOperand> createFenceArg(unsigned Val, SMLoc S) { auto Op = std::make_unique<RISCVOperand>(KindTy::Fence); Op->Fence.Val = Val; @@ -1315,6 +1361,11 @@ struct RISCVOperand final : public MCParsedAsmOperand { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(getFRM())); } + + void addSMTVTypeOperand(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createImm(getSMTVType())); + } }; } // end anonymous namespace. @@ -1349,6 +1400,8 @@ static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg, unsigned RegClassID; if (Kind == MCK_VRM2) RegClassID = RISCV::VRM2RegClassID; + else if (Kind == MCK_VRM2NoV0) + RegClassID = RISCV::VRM2NoV0RegClassID; else if (Kind == MCK_VRM4) RegClassID = RISCV::VRM4RegClassID; else if (Kind == MCK_VRM8) @@ -1423,7 +1476,8 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, // As the parser couldn't differentiate an VRM2/VRM4/VRM8 from an VR, coerce // the register from VR to VRM2/VRM4/VRM8 if necessary. - if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8)) { + if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM2NoV0 || + Kind == MCK_VRM4 || Kind == MCK_VRM8)) { Op.Reg.Reg = convertVRToVRMx(*getContext().getRegisterInfo(), Reg, Kind); if (!Op.Reg.Reg) return Match_InvalidOperand; @@ -2664,6 +2718,26 @@ ParseStatus RISCVAsmParser::parseGPRPair(OperandVector &Operands, return ParseStatus::Success; } +ParseStatus RISCVAsmParser::parseSMTVType(OperandVector &Operands) { + if (getLexer().isNot(AsmToken::Identifier)) + return TokError("operand must be a valid SpacemiT VType mnemonic"); + + StringRef Str = getLexer().getTok().getIdentifier(); + XSMTVTypeMode::SMTVTypeMode VType = XSMTVTypeMode::stringToSMTVTypeMode(Str); + + if (!isValidSMTVTypeMode(VType)) + return TokError("SpacemiT AI only support [i4|i8|bfp16|fp16] Mode"); + + // bfp16 and fp16 has the same encoding in SpacemiT AI + // In AsmParse, need conside bfp16 as fp16 + if (VType == XSMTVTypeMode::SMTVTypeMode::SMT_BFP16) { + VType = XSMTVTypeMode::SMTVTypeMode::SMT_FP16; + } + Operands.push_back(RISCVOperand::createSMTVType(VType, getLoc())); + Lex(); // Eat identifier token. + return ParseStatus::Success; +} + ParseStatus RISCVAsmParser::parseFRMArg(OperandVector &Operands) { if (getLexer().isNot(AsmToken::Identifier)) return TokError( @@ -2681,6 +2755,11 @@ ParseStatus RISCVAsmParser::parseFRMArg(OperandVector &Operands) { return ParseStatus::Success; } +std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultSMTVType() { + return RISCVOperand::createSMTVType(XSMTVTypeMode::SMTVTypeMode::SMT_I8, + llvm::SMLoc()); +} + ParseStatus RISCVAsmParser::parseFenceArg(OperandVector &Operands) { const AsmToken &Tok = getLexer().getTok(); diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 70d40c2355f4f..a6f71f12ae675 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -217,6 +217,35 @@ static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } +static DecodeStatus DecodeVRV0V1RegisterClass(MCInst &Inst, uint32_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + if (RegNo >= 2) + return MCDisassembler::Fail; + + return DecodeSimpleRegisterClass<RISCV::V0, 2>(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeVRNoV0V1RegisterClass(MCInst &Inst, uint32_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + if (RegNo == 0 || RegNo == 1) + return MCDisassembler::Fail; + + return DecodeSimpleRegisterClass<RISCV::V0, 32>(Inst, RegNo, Address, + Decoder); +} + +static DecodeStatus DecodeVRM2NoV0RegisterClass(MCInst &Inst, uint32_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + if (RegNo == 0) + return MCDisassembler::Fail; + + return DecodeVectorRegisterClass<RISCV::VRM2RegClassID, 32, 2>( + Inst, RegNo, Address, Decoder); +} + static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { @@ -531,7 +560,8 @@ static constexpr FeatureBitset XAndesGroup = { RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH, RISCV::FeatureVendorXAndesVDot}; -static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot}; +static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot, + RISCV::FeatureVendorXSMTVDotII}; static constexpr FeatureBitset XAIFGroup = {RISCV::FeatureVendorXAIFET}; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index 7f1aa83075f1f..89528f75933ff 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -140,6 +140,8 @@ enum OperandType : unsigned { OPERAND_BCC_OPCODE, OPERAND_VMASK, + OPERAND_SMTVType, + OPERAND_SMTI8, }; } // namespace RISCVOp @@ -548,6 +550,66 @@ inline static bool isValidRoundingMode(unsigned Mode) { } } // namespace RISCVFPRndMode +namespace XSMTVTypeMode { +enum SMTVTypeMode { + // Define the different SMT VType modes here + SMT_FP16 = 0, + SMT_BFP16 = 1, + SMT_I4 = 2, + SMT_I8 = 3, + Invalid +}; + +inline static StringRef SMTVTypeModeToString(SMTVTypeMode TypeMode) { + switch (TypeMode) { + default: + llvm_unreachable("Unknown SpacemiT AI VType's mode"); + case XSMTVTypeMode::SMT_BFP16: + return "bfp16"; + case XSMTVTypeMode::SMT_FP16: + return "fp16"; + case XSMTVTypeMode::SMT_I4: + return "i4"; + case XSMTVTypeMode::SMT_I8: + return "i8"; + } +} + +inline static SMTVTypeMode stringToSMTVTypeMode(StringRef Str) { + return StringSwitch<SMTVTypeMode>(Str) + .Case("bfp16", XSMTVTypeMode::SMT_BFP16) + .Case("fp16", XSMTVTypeMode::SMT_FP16) + .Case("i4", XSMTVTypeMode::SMT_I4) + .Case("i8", XSMTVTypeMode::SMT_I8) + .Default(XSMTVTypeMode::Invalid); +} + +inline static bool isValidSMTVTypeInt(unsigned Mode) { + switch (Mode) { + default: + return false; + case XSMTVTypeMode::SMT_I4: + case XSMTVTypeMode::SMT_I8: + return true; + } +} + +inline static bool isValidSMTVTypeFP(unsigned Mode) { + switch (Mode) { + default: + return false; + case XSMTVTypeMode::SMT_BFP16: + case XSMTVTypeMode::SMT_FP16: + return true; + } +} + +inline static bool isValidSMTVTypeMode(unsigned Mode) { + return isValidSMTVTypeInt(Mode) || isValidSMTVTypeFP(Mode); +} + +} // namespace XSMTVTypeMode + namespace RISCVVXRndMode { enum RoundingMode { RNU = 0, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index aa7ce5bf5e2a2..1e1be42540397 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -161,6 +161,16 @@ void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo, O << "0"; } +void RISCVInstPrinter::printSMTVType(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + auto VType = + static_cast<XSMTVTypeMode::SMTVTypeMode>(MI->getOperand(OpNo).getImm()); + assert(XSMTVTypeMode::isValidSMTVTypeMode(VType) && + "SpacemiT AI only support [i4|i8|fp16|bfp16] Mode"); + O << ", " << XSMTVTypeMode::SMTVTypeModeToString(VType); +} + void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { auto FRMArg = diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h index fb0598faff2be..aac5ac29c7747 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -38,6 +38,8 @@ class RISCVInstPrinter : public MCInstPrinter { const MCSubtargetInfo &STI, raw_ostream &O); void printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); + void printSMTVType(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printFRMArgLegacy(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 93392c1b3d402..d3fbd92dbf806 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1799,6 +1799,14 @@ def HasVendorXSMTVDot AssemblerPredicate<(all_of FeatureVendorXSMTVDot), "'XSMTVDot' (SpacemiT Vector Dot Product Extension)">; +def FeatureVendorXSMTVDotII + : RISCVExtension<1, 0, "SpacemiT Vector Dot Product 2.0 Extension", + [FeatureStdExtZve32f]>; +def HasVendorXSMTVDotII + : Predicate<"Subtarget->hasVendorXSMTVDotII()">, + AssemblerPredicate<(all_of FeatureVendorXSMTVDotII), + "'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0))">; + def FeatureVendorXAIFET : RISCVExtension<1, 0, "AI Foundry ET Extension", [FeatureStdExtF]>; def HasXAIFET : Predicate<"Subtarget->hasXAIFET()">, diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td index e3c93dc93a686..d48de5cc0f394 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -58,6 +58,7 @@ def InstFormatQC_EB : InstFormat<24>; def InstFormatQC_EJ : InstFormat<25>; def InstFormatQC_ES : InstFormat<26>; def InstFormatNDS_BRANCH_10 : InstFormat<27>; +def InstFormatSMT : InstFormat<28>; def InstFormatOther : InstFormat<31>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td index 66535c4e77f4a..aa3e515a8a464 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td @@ -54,6 +54,60 @@ defvar SlideEncodes = [SlideEncode<0b00, "1">, SlideEncode<0b01, "2">, SlideEncode<0b10, "3">]; +class HPEncode<bits<3> encoding, string name> { + bits<3> Encoding = encoding; + string Name = name; +} +defvar HPEncodes = [HPEncode<0b011, "u">, + HPEncode<0b110, "us">, + HPEncode<0b101, "su">, + HPEncode<0b100, "">]; + +// The SpacemiT support element Type +class SMTVType<bit isFP> : AsmOperandClass { + let Name = "SMTVType"#isFP; + let RenderMethod = "addSMTVTypeOperand"; + let ParserMethod = "parseSMTVType"; + let DiagnosticType = "InvalidSMTType"#isFP; + let DiagnosticString = !if(isFP, + "This Inst only supports bfp16 and fp16", + "This Inst only supports i4 and i8, i8 is defuat type" + ); + let IsOptional = 1; + let DefaultMethod = "defaultSMTVType"; +} + +class SMT_VTYPE<bit isFP> : Operand<XLenVT> { + let ParserMatchClass = SMTVType<isFP>; + let PrintMethod = "printSMTVType"; + let DecoderMethod = "decodeUImmOperand<2>"; + let OperandType = "OPERAND_SMTVType"; + let OperandNamespace = "RISCVOp"; +} + +// Supports i4 and i8 +def SMT_INT : SMT_VTYPE<0>; +// Supports bfp16 and fp16 +def SMT_FP : SMT_VTYPE<1>; + +def SMTI8 : AsmOperandClass { + let Name = "SMTI8"; + let RenderMethod = "addSMTVTypeOperand"; + let DiagnosticType = "InvalidSMTI8"; + let DiagnosticString = "smt.vmadot with slide only support i8 type"; + let ParserMethod = "parseSMTVType"; + let IsOptional = 1; + let DefaultMethod = "defaultSMTVType"; +} + +def SMT_I8 : Operand<XLenVT> { + let ParserMatchClass = SMTI8; + let PrintMethod = "printSMTVType"; + let DecoderMethod = "decodeUImmOperand<2>"; + let OperandType = "OPERAND_SMTI8"; + let OperandNamespace = "RISCVOp"; +} + //===----------------------------------------------------------------------===// // Instruction formats //===----------------------------------------------------------------------===// @@ -62,7 +116,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { // Base vector dot product (no slide) format. class SMTVMADot<bits<2> sign, string opcodestr, bit EarlyClobber = 0> : RVInst<(outs VRM2:$vd_wb), (ins VRM2:$vd, VR:$vs1, VR:$vs2), - opcodestr, "$vd, $vs1, $vs2", [], InstFormatR> { + opcodestr, "$vd, $vs1, $vs2", [], InstFormatSMT>... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/202533 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
