https://github.com/LiqinWeng updated https://github.com/llvm/llvm-project/pull/202533
>From d9f30a61d4b6db5f42451c54e97a00b52bc78e05 Mon Sep 17 00:00:00 2001 From: wengliqin <[email protected]> Date: Tue, 9 Jun 2026 16:06:46 +0800 Subject: [PATCH 1/2] [RISCV] Support spacemit vsmtvdotii externsions SPEC: https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md --- .../Driver/print-supported-extensions-riscv.c | 1 + clang/test/Driver/riscv-cpus.c | 1 + llvm/docs/RISCVUsage.rst | 4 + .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 81 ++++++- .../RISCV/Disassembler/RISCVDisassembler.cpp | 32 ++- .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 62 ++++++ .../RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 10 + .../RISCV/MCTargetDesc/RISCVInstPrinter.h | 2 + llvm/lib/Target/RISCV/RISCVFeatures.td | 8 + llvm/lib/Target/RISCV/RISCVInstrFormats.td | 1 + .../RISCV/RISCVInstrFormatsSpacemitV.td | 202 +++++++++++++++++- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 6 + .../Target/RISCV/RISCVInstrInfoXSpacemiT.td | 62 ++++++ llvm/lib/Target/RISCV/RISCVProcessors.td | 3 +- llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 4 + llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/MC/RISCV/xsmtvdot-valid.s | 32 +-- .../TargetParser/RISCVISAInfoTest.cpp | 1 + 18 files changed, 491 insertions(+), 22 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 29731e565ecfc..3ea2b846ee5d5 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -228,6 +228,7 @@ // CHECK-NEXT: xsifivecdiscarddlone 1.0 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction) // CHECK-NEXT: xsifivecflushdlone 1.0 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction) // CHECK-NEXT: xsmtvdot 1.0 'XSMTVDot' (SpacemiT Vector Dot Product Extension) +// CHECK-NEXT: xsmtvdotii 1.0 'XSMTVDotII' (SpacemiT Vector Dot Product 2.0 Extension) // CHECK-NEXT: xtheadba 1.0 'XTHeadBa' (T-Head address calculation instructions) // CHECK-NEXT: xtheadbb 1.0 'XTHeadBb' (T-Head basic bit-manipulation instructions) // CHECK-NEXT: xtheadbs 1.0 'XTHeadBs' (T-Head single-bit instructions) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 99a4c0601b41b..dffdf8dbda9a6 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -106,6 +106,7 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-a100 | FileCheck -check-prefix=MCPU-SPACEMIT-A100 %s // MCPU-SPACEMIT-A100: "-target-cpu" "spacemit-a100" // COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-spacemit-a100.c` +// MCPU-SPACEMIT-A100-SAME: "-target-feature" "+xsmtvdotii" // MCPU-SPACEMIT-A100-SAME: "-target-abi" "lp64d" // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=spacemit-a100 | FileCheck -check-prefix=MTUNE-SPACEMIT-A100 %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 166b5dd6352db..8d1ab1fa914b3 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -575,6 +575,10 @@ The current vendor extensions supported are: SpacemiT defines `Integrated Matrix Extension (IME) specification <https://github.com/spacemit-com/riscv-ime-extension-spec/releases/tag/v1.0>`__. LLVM implement the hardware-adapted subset for SpacemiT X60, defined in the `feature document <https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1>`__ by SpacemiT. All instructions are prefixed with `smt.` as described in the implementation guide. Note that this implemented subset is `version 1.0.0 of the SpacemiT Vector Dot Product Extension specification`, which is strictly a subset of the full IME specification to reflect the capabilities of SpacemiT X60 hardware correctly. +``XSMTVDotII`` + SpacemiT defines `https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md`. + LLVM implement the hardware-adapted subset for SpacemiT A100 + Experimental C Intrinsics ========================= diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 93fb1fa5a889f..5b603b7bb4482 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -215,6 +215,7 @@ class RISCVAsmParser : public MCTargetAsmParser { template <bool IsRV64Inst> ParseStatus parseGPRPair(OperandVector &Operands); ParseStatus parseGPRPair(OperandVector &Operands, bool IsRV64Inst); ParseStatus parseFRMArg(OperandVector &Operands); + ParseStatus parseSMTVType(OperandVector &Operands); ParseStatus parseFenceArg(OperandVector &Operands); ParseStatus parseRegList(OperandVector &Operands, bool MustIncludeS0 = false); ParseStatus parseRegListS0(OperandVector &Operands) { @@ -289,6 +290,7 @@ class RISCVAsmParser : public MCTargetAsmParser { std::unique_ptr<RISCVOperand> defaultMaskRegOp() const; std::unique_ptr<RISCVOperand> defaultFRMArgOp() const; std::unique_ptr<RISCVOperand> defaultFRMArgLegacyOp() const; + std::unique_ptr<RISCVOperand> defaultSMTVType(); public: enum RISCVMatchResultTy : unsigned { @@ -348,6 +350,7 @@ struct RISCVOperand final : public MCParsedAsmOperand { FPImmediate, SystemRegister, VType, + SMTVType, FRM, Fence, RegList, @@ -381,6 +384,10 @@ struct RISCVOperand final : public MCParsedAsmOperand { unsigned Val; }; + struct SMTVTypeOp { + XSMTVTypeMode::SMTVTypeMode SMTVType; + }; + struct FRMOp { RISCVFPRndMode::RoundingMode FRM; }; @@ -410,6 +417,7 @@ struct RISCVOperand final : public MCParsedAsmOperand { FPImmOp FPImm; SysRegOp SysReg; VTypeOp VType; + SMTVTypeOp SMTVType; FRMOp FRM; FenceOp Fence; RegListOp RegList; @@ -443,6 +451,9 @@ struct RISCVOperand final : public MCParsedAsmOperand { case KindTy::VType: VType = o.VType; break; + case KindTy::SMTVType: + SMTVType = o.SMTVType; + break; case KindTy::FRM: FRM = o.FRM; break; @@ -653,6 +664,22 @@ struct RISCVOperand final : public MCParsedAsmOperand { bool isFRMArgLegacy() const { return Kind == KindTy::FRM; } bool isRTZArg() const { return isFRMArg() && FRM.FRM == RISCVFPRndMode::RTZ; } + // Return true if the operand is a SpacemiT AI Inst support i4/i8 + bool isSMTVType0() const { + return Kind == KindTy::SMTVType && + XSMTVTypeMode::isValidSMTVTypeInt(SMTVType.SMTVType); + } + + // Return true if the operand is a SpacemiT AI Inst support bfp16/fp16 + bool isSMTVType1() const { + return Kind == KindTy::SMTVType && + XSMTVTypeMode::isValidSMTVTypeFP(SMTVType.SMTVType); + } + + bool isSMTI8() const { + return isSMTVType0() && SMTVType.SMTVType == XSMTVTypeMode::SMT_I8; + } + /// Return true if the operand is a valid fli.s floating-point immediate. bool isLoadFPImm() const { if (isExpr()) @@ -1069,6 +1096,11 @@ struct RISCVOperand final : public MCParsedAsmOperand { return Fence.Val; } + XSMTVTypeMode::SMTVTypeMode getSMTVType() const { + assert(Kind == KindTy::SMTVType && "Invalid type access!"); + return SMTVType.SMTVType; + } + void print(raw_ostream &OS, const MCAsmInfo &MAI) const override { auto RegName = [](MCRegister Reg) { if (Reg) @@ -1106,6 +1138,11 @@ struct RISCVOperand final : public MCParsedAsmOperand { OS << roundingModeToString(getFRM()); OS << '>'; break; + case KindTy::SMTVType: + OS << "<smt: "; + SMTVTypeModeToString(getSMTVType()); + OS << '>'; + break; case KindTy::Fence: OS << "<fence: "; OS << getFence(); @@ -1184,6 +1221,15 @@ struct RISCVOperand final : public MCParsedAsmOperand { return Op; } + static std::unique_ptr<RISCVOperand> + createSMTVType(XSMTVTypeMode::SMTVTypeMode VType, SMLoc S) { + auto Op = std::make_unique<RISCVOperand>(KindTy::SMTVType); + Op->SMTVType.SMTVType = VType; + Op->StartLoc = S; + Op->EndLoc = S; + return Op; + } + static std::unique_ptr<RISCVOperand> createFenceArg(unsigned Val, SMLoc S) { auto Op = std::make_unique<RISCVOperand>(KindTy::Fence); Op->Fence.Val = Val; @@ -1315,6 +1361,11 @@ struct RISCVOperand final : public MCParsedAsmOperand { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(getFRM())); } + + void addSMTVTypeOperand(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::createImm(getSMTVType())); + } }; } // end anonymous namespace. @@ -1349,6 +1400,8 @@ static MCRegister convertVRToVRMx(const MCRegisterInfo &RI, MCRegister Reg, unsigned RegClassID; if (Kind == MCK_VRM2) RegClassID = RISCV::VRM2RegClassID; + else if (Kind == MCK_VRM2NoV0) + RegClassID = RISCV::VRM2NoV0RegClassID; else if (Kind == MCK_VRM4) RegClassID = RISCV::VRM4RegClassID; else if (Kind == MCK_VRM8) @@ -1423,7 +1476,8 @@ unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, // As the parser couldn't differentiate an VRM2/VRM4/VRM8 from an VR, coerce // the register from VR to VRM2/VRM4/VRM8 if necessary. - if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM4 || Kind == MCK_VRM8)) { + if (IsRegVR && (Kind == MCK_VRM2 || Kind == MCK_VRM2NoV0 || + Kind == MCK_VRM4 || Kind == MCK_VRM8)) { Op.Reg.Reg = convertVRToVRMx(*getContext().getRegisterInfo(), Reg, Kind); if (!Op.Reg.Reg) return Match_InvalidOperand; @@ -2664,6 +2718,26 @@ ParseStatus RISCVAsmParser::parseGPRPair(OperandVector &Operands, return ParseStatus::Success; } +ParseStatus RISCVAsmParser::parseSMTVType(OperandVector &Operands) { + if (getLexer().isNot(AsmToken::Identifier)) + return TokError("operand must be a valid SpacemiT VType mnemonic"); + + StringRef Str = getLexer().getTok().getIdentifier(); + XSMTVTypeMode::SMTVTypeMode VType = XSMTVTypeMode::stringToSMTVTypeMode(Str); + + if (!isValidSMTVTypeMode(VType)) + return TokError("SpacemiT AI only support [i4|i8|bfp16|fp16] Mode"); + + // bfp16 and fp16 has the same encoding in SpacemiT AI + // In AsmParse, need conside bfp16 as fp16 + if (VType == XSMTVTypeMode::SMTVTypeMode::SMT_BFP16) { + VType = XSMTVTypeMode::SMTVTypeMode::SMT_FP16; + } + Operands.push_back(RISCVOperand::createSMTVType(VType, getLoc())); + Lex(); // Eat identifier token. + return ParseStatus::Success; +} + ParseStatus RISCVAsmParser::parseFRMArg(OperandVector &Operands) { if (getLexer().isNot(AsmToken::Identifier)) return TokError( @@ -2681,6 +2755,11 @@ ParseStatus RISCVAsmParser::parseFRMArg(OperandVector &Operands) { return ParseStatus::Success; } +std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultSMTVType() { + return RISCVOperand::createSMTVType(XSMTVTypeMode::SMTVTypeMode::SMT_I8, + llvm::SMLoc()); +} + ParseStatus RISCVAsmParser::parseFenceArg(OperandVector &Operands) { const AsmToken &Tok = getLexer().getTok(); diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 70d40c2355f4f..a6f71f12ae675 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -217,6 +217,35 @@ static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } +static DecodeStatus DecodeVRV0V1RegisterClass(MCInst &Inst, uint32_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + if (RegNo >= 2) + return MCDisassembler::Fail; + + return DecodeSimpleRegisterClass<RISCV::V0, 2>(Inst, RegNo, Address, Decoder); +} + +static DecodeStatus DecodeVRNoV0V1RegisterClass(MCInst &Inst, uint32_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + if (RegNo == 0 || RegNo == 1) + return MCDisassembler::Fail; + + return DecodeSimpleRegisterClass<RISCV::V0, 32>(Inst, RegNo, Address, + Decoder); +} + +static DecodeStatus DecodeVRM2NoV0RegisterClass(MCInst &Inst, uint32_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + if (RegNo == 0) + return MCDisassembler::Fail; + + return DecodeVectorRegisterClass<RISCV::VRM2RegClassID, 32, 2>( + Inst, RegNo, Address, Decoder); +} + static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { @@ -531,7 +560,8 @@ static constexpr FeatureBitset XAndesGroup = { RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH, RISCV::FeatureVendorXAndesVDot}; -static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot}; +static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot, + RISCV::FeatureVendorXSMTVDotII}; static constexpr FeatureBitset XAIFGroup = {RISCV::FeatureVendorXAIFET}; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index 7f1aa83075f1f..89528f75933ff 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -140,6 +140,8 @@ enum OperandType : unsigned { OPERAND_BCC_OPCODE, OPERAND_VMASK, + OPERAND_SMTVType, + OPERAND_SMTI8, }; } // namespace RISCVOp @@ -548,6 +550,66 @@ inline static bool isValidRoundingMode(unsigned Mode) { } } // namespace RISCVFPRndMode +namespace XSMTVTypeMode { +enum SMTVTypeMode { + // Define the different SMT VType modes here + SMT_FP16 = 0, + SMT_BFP16 = 1, + SMT_I4 = 2, + SMT_I8 = 3, + Invalid +}; + +inline static StringRef SMTVTypeModeToString(SMTVTypeMode TypeMode) { + switch (TypeMode) { + default: + llvm_unreachable("Unknown SpacemiT AI VType's mode"); + case XSMTVTypeMode::SMT_BFP16: + return "bfp16"; + case XSMTVTypeMode::SMT_FP16: + return "fp16"; + case XSMTVTypeMode::SMT_I4: + return "i4"; + case XSMTVTypeMode::SMT_I8: + return "i8"; + } +} + +inline static SMTVTypeMode stringToSMTVTypeMode(StringRef Str) { + return StringSwitch<SMTVTypeMode>(Str) + .Case("bfp16", XSMTVTypeMode::SMT_BFP16) + .Case("fp16", XSMTVTypeMode::SMT_FP16) + .Case("i4", XSMTVTypeMode::SMT_I4) + .Case("i8", XSMTVTypeMode::SMT_I8) + .Default(XSMTVTypeMode::Invalid); +} + +inline static bool isValidSMTVTypeInt(unsigned Mode) { + switch (Mode) { + default: + return false; + case XSMTVTypeMode::SMT_I4: + case XSMTVTypeMode::SMT_I8: + return true; + } +} + +inline static bool isValidSMTVTypeFP(unsigned Mode) { + switch (Mode) { + default: + return false; + case XSMTVTypeMode::SMT_BFP16: + case XSMTVTypeMode::SMT_FP16: + return true; + } +} + +inline static bool isValidSMTVTypeMode(unsigned Mode) { + return isValidSMTVTypeInt(Mode) || isValidSMTVTypeFP(Mode); +} + +} // namespace XSMTVTypeMode + namespace RISCVVXRndMode { enum RoundingMode { RNU = 0, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index aa7ce5bf5e2a2..1e1be42540397 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -161,6 +161,16 @@ void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo, O << "0"; } +void RISCVInstPrinter::printSMTVType(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + auto VType = + static_cast<XSMTVTypeMode::SMTVTypeMode>(MI->getOperand(OpNo).getImm()); + assert(XSMTVTypeMode::isValidSMTVTypeMode(VType) && + "SpacemiT AI only support [i4|i8|fp16|bfp16] Mode"); + O << ", " << XSMTVTypeMode::SMTVTypeModeToString(VType); +} + void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { auto FRMArg = diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h index fb0598faff2be..aac5ac29c7747 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -38,6 +38,8 @@ class RISCVInstPrinter : public MCInstPrinter { const MCSubtargetInfo &STI, raw_ostream &O); void printFenceArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); + void printSMTVType(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printFRMArgLegacy(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 93392c1b3d402..d3fbd92dbf806 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1799,6 +1799,14 @@ def HasVendorXSMTVDot AssemblerPredicate<(all_of FeatureVendorXSMTVDot), "'XSMTVDot' (SpacemiT Vector Dot Product Extension)">; +def FeatureVendorXSMTVDotII + : RISCVExtension<1, 0, "SpacemiT Vector Dot Product 2.0 Extension", + [FeatureStdExtZve32f]>; +def HasVendorXSMTVDotII + : Predicate<"Subtarget->hasVendorXSMTVDotII()">, + AssemblerPredicate<(all_of FeatureVendorXSMTVDotII), + "'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0))">; + def FeatureVendorXAIFET : RISCVExtension<1, 0, "AI Foundry ET Extension", [FeatureStdExtF]>; def HasXAIFET : Predicate<"Subtarget->hasXAIFET()">, diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td index e3c93dc93a686..d48de5cc0f394 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -58,6 +58,7 @@ def InstFormatQC_EB : InstFormat<24>; def InstFormatQC_EJ : InstFormat<25>; def InstFormatQC_ES : InstFormat<26>; def InstFormatNDS_BRANCH_10 : InstFormat<27>; +def InstFormatSMT : InstFormat<28>; def InstFormatOther : InstFormat<31>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td index 66535c4e77f4a..aa3e515a8a464 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td @@ -54,6 +54,60 @@ defvar SlideEncodes = [SlideEncode<0b00, "1">, SlideEncode<0b01, "2">, SlideEncode<0b10, "3">]; +class HPEncode<bits<3> encoding, string name> { + bits<3> Encoding = encoding; + string Name = name; +} +defvar HPEncodes = [HPEncode<0b011, "u">, + HPEncode<0b110, "us">, + HPEncode<0b101, "su">, + HPEncode<0b100, "">]; + +// The SpacemiT support element Type +class SMTVType<bit isFP> : AsmOperandClass { + let Name = "SMTVType"#isFP; + let RenderMethod = "addSMTVTypeOperand"; + let ParserMethod = "parseSMTVType"; + let DiagnosticType = "InvalidSMTType"#isFP; + let DiagnosticString = !if(isFP, + "This Inst only supports bfp16 and fp16", + "This Inst only supports i4 and i8, i8 is defuat type" + ); + let IsOptional = 1; + let DefaultMethod = "defaultSMTVType"; +} + +class SMT_VTYPE<bit isFP> : Operand<XLenVT> { + let ParserMatchClass = SMTVType<isFP>; + let PrintMethod = "printSMTVType"; + let DecoderMethod = "decodeUImmOperand<2>"; + let OperandType = "OPERAND_SMTVType"; + let OperandNamespace = "RISCVOp"; +} + +// Supports i4 and i8 +def SMT_INT : SMT_VTYPE<0>; +// Supports bfp16 and fp16 +def SMT_FP : SMT_VTYPE<1>; + +def SMTI8 : AsmOperandClass { + let Name = "SMTI8"; + let RenderMethod = "addSMTVTypeOperand"; + let DiagnosticType = "InvalidSMTI8"; + let DiagnosticString = "smt.vmadot with slide only support i8 type"; + let ParserMethod = "parseSMTVType"; + let IsOptional = 1; + let DefaultMethod = "defaultSMTVType"; +} + +def SMT_I8 : Operand<XLenVT> { + let ParserMatchClass = SMTI8; + let PrintMethod = "printSMTVType"; + let DecoderMethod = "decodeUImmOperand<2>"; + let OperandType = "OPERAND_SMTI8"; + let OperandNamespace = "RISCVOp"; +} + //===----------------------------------------------------------------------===// // Instruction formats //===----------------------------------------------------------------------===// @@ -62,7 +116,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { // Base vector dot product (no slide) format. class SMTVMADot<bits<2> sign, string opcodestr, bit EarlyClobber = 0> : RVInst<(outs VRM2:$vd_wb), (ins VRM2:$vd, VR:$vs1, VR:$vs2), - opcodestr, "$vd, $vs1, $vs2", [], InstFormatR> { + opcodestr, "$vd, $vs1, $vs2", [], InstFormatSMT> { bits<5> vd; bits<5> vs1; bits<5> vs2; @@ -83,7 +137,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class SMTVMADotSlide<bits<2> funct2, bits<2> sign, string opcodestr, bit EarlyClobber = 0> : RVInst<(outs VRM2:$vd_wb), (ins VRM2:$vd, VRM2:$vs1, VR:$vs2), - opcodestr, "$vd, $vs1, $vs2", [], InstFormatR> { + opcodestr, "$vd, $vs1, $vs2", [], InstFormatSMT> { bits<5> vd; bits<5> vs1; bits<5> vs2; @@ -99,5 +153,147 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { !if(EarlyClobber, "@earlyclobber $vd_wb, $vd = $vd_wb", "$vd = $vd_wb"); let UseNamedOperandTable = true; } -} + class SMTVMADotII<bits<2> sign, string opcodestr, bit EarlyClobber = 0> + : RVInst<(outs VRM2:$vd_wb), + (ins VRM2:$vd, VR:$vs1, VR:$vs2, SMT_INT:$vtype), opcodestr, + "$vd, $vs1, $vs2$vtype", [], InstFormatSMT> { + bits<5> vd; + bits<5> vs1; + bits<5> vs2; + bits<2> vtype; + + let Inst{31} = 0b1; + let Inst{30-29} = vtype; + let Inst{28-25} = 0b0001; + let Inst{24-20} = vs2; + let Inst{19-15} = vs1; + let Inst{14} = 0b0; + let Inst{13-12} = sign; + let Inst{11-7} = vd; + let Inst{6-0} = OPC_CUSTOM_1.Value; + let Constraints = + !if(EarlyClobber, "@earlyclobber $vd_wb, $vd = $vd_wb", "$vd = $vd_wb"); + let UseNamedOperandTable = true; + } + + // Now only support element type i8 for sliding-window dot-product + // instructions + class SMTVMADotSlideII<bits<2> slide, bits<2> sign, string opcodestr, + bit EarlyClobber = 0> + : RVInst<(outs VRM2:$vd_wb), + (ins VRM2:$vd, VRM2:$vs1, VR:$vs2, SMT_I8:$vtype), opcodestr, + "$vd, $vs1, $vs2$vtype", [], InstFormatSMT> { + bits<5> vd; + bits<5> vs1; + bits<5> vs2; + bits<2> vtype; + + let Inst{31} = 1; + let Inst{30-29} = vtype; + let Inst{28-25} = 0b0011; + let Inst{24-20} = vs2; + let Inst{19-16} = vs1{4-1}; + let Inst{15-14} = slide; + let Inst{13-12} = sign; + let Inst{11-7} = vd; + let Inst{6-0} = OPC_CUSTOM_1.Value; + let Constraints = + !if(EarlyClobber, "@earlyclobber $vd_wb, $vd = $vd_wb", "$vd = $vd_wb"); + let UseNamedOperandTable = true; + } + + class SMTVMADOTSP<bits<2> sign, string opcodestr, string argstr, + bit EarlyClobber = 0> + : RVInst<(outs VRM2NoV0:$vd_wb), + (ins VRM2NoV0:$vd, VRM2NoV0:$vs1, VRNoV0V1:$vs2, VRV0V1:$vmask, uimm2:$imm2, + SMT_INT:$vtype), + opcodestr, argstr, [], InstFormatSMT> { + bits<5> vd; + bits<5> vs1; + bits<5> vs2; + bits<2> vtype; + bit vmask; + bits<2> imm2; + + let Inst{31} = 0b1; + let Inst{30-29} = vtype; + let Inst{28-26} = 0b010; + let Inst{25} = vmask; + let Inst{24-20} = vs2; + let Inst{19-16} = vs1{4-1}; + let Inst{15} = imm2{1}; + let Inst{14} = 0b0; + let Inst{13-12} = sign; + let Inst{11-8} = vd{4-1}; + let Inst{7} = imm2{0}; + let Inst{6-0} = OPC_CUSTOM_1.Value; + let Constraints = + !if(EarlyClobber, "@earlyclobber $vd_wb, $vd = $vd_wb", "$vd = $vd_wb"); + let UseNamedOperandTable = true; + } + + class SMTVMADOTHP<bits<3> funct3, string opcodestr, string argstr, + bit EarlyClobber = 0> + : RVInst<(outs VRNoV0V1:$vd_wb), + (ins VRNoV0V1:$vd, VRNoV0V1:$vs1, VRNoV0V1:$vs2, VRV0V1:$vmask, uimm3:$imm3, + SMT_INT:$vtype), + opcodestr, argstr, [], InstFormatSMT> { + bits<5> vd; + bits<5> vs1; + bits<5> vs2; + bits<2> vtype; + bit vmask; + bits<3> imm3; + + let Inst{31} = 0b1; + let Inst{30-29} = vtype; + let Inst{28-26} = funct3; + let Inst{25} = vmask; + let Inst{24-20} = vs2; + let Inst{19-15} = vs1; + let Inst{14-12} = imm3; + let Inst{11-7} = vd; + let Inst{6-0} = OPC_CUSTOM_1.Value; + let Constraints = + !if(EarlyClobber, "@earlyclobber $vd_wb, $vd = $vd_wb", "$vd = $vd_wb"); + let UseNamedOperandTable = true; + } + + class SMTVFWMADOT<bits<3> funct3, dag outs, dag ins, string opcodestr, + string argstr> + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatSMT> { + bits<5> vd; + bits<5> vs1; + bits<5> vs2; + bits<2> vtype; + + let Inst{31} = 0b1; + let Inst{30-29} = vtype; + let Inst{28-25} = 0b1111; + let Inst{24-20} = vs2; + let Inst{19-15} = vs1; + let Inst{14-12} = funct3; + let Inst{11-7} = vd; + let Inst{6-0} = OPC_CUSTOM_1.Value; + let UseNamedOperandTable = true; + } + + class SMTVPACK<bits<7> funct7, bit funct1, dag outs, dag ins, + string opcodestr, string argstr> + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatSMT> { + bits<5> vd; + bits<5> vs1; + bits<5> vs2; + bits<2> imm2; + + let Inst{31-25} = funct7; + let Inst{24-20} = vs2; + let Inst{19-15} = vs1; + let Inst{14} = funct1; + let Inst{13-12} = imm2; + let Inst{11-7} = vd; + let Inst{6-0} = OPC_CUSTOM_1.Value; + let UseNamedOperandTable = true; + } +} diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index e41140907282b..bda1a9770d868 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3138,6 +3138,12 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, case RISCVOp::OPERAND_RTZARG: Ok = Imm == RISCVFPRndMode::RTZ; break; + case RISCVOp::OPERAND_SMTVType: + Ok = XSMTVTypeMode::isValidSMTVTypeMode(Imm); + break; + case RISCVOp::OPERAND_SMTI8: + Ok = Imm == XSMTVTypeMode::SMT_I8; + break; case RISCVOp::OPERAND_COND_CODE: Ok = Imm >= 0 && Imm < RISCVCC::COND_INVALID; break; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td index 41a0f0b73c1fc..d28ce0b505675 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td @@ -46,4 +46,66 @@ let DecoderNamespace = "XSMT" in { def SMT_VMADOT#!toupper(a.Name)#!toupper(b.Name) : SMTVMADotSlide<a.Encoding, b.Encoding, "smt.vmadot"#a.Name#b.Name>, Sched<[]>; } + + class VFWMADTSLIDE_INSN<bits<3> funct3, string opcodestr> + : SMTVFWMADOT<funct3, (outs VRM2:$vd_wb), + (ins VRM2:$vd, VRM2:$vs1, VR:$vs2, SMT_FP:$vtype), + opcodestr, "$vd, $vs1, $vs2$vtype">, Sched<[]>; + + class VNPACK_INSN<bits<7> funct7, bit funct1, string opcodestr> + : SMTVPACK<funct7, funct1, (outs VR:$vd), + (ins VR:$vs1, VR:$vs2, uimm2:$imm2), opcodestr, + "$vd, $vs1, $vs2, $imm2">, Sched<[]>; + + class VPACK_INSN<bits<7> funct7, bit funct1, string opcodestr> + : SMTVPACK<funct7, funct1, (outs VRM2:$vd), + (ins VR:$vs1, VR:$vs2, uimm2:$imm2), opcodestr, + "$vd, $vs1, $vs2, $imm2">, Sched<[]>; + + let Predicates = [HasVendorXSMTVDotII, IsRV64], ElementsDependOn = EltDepsNone in { + let VS1VS2Constraint = WidenV in { + // Base VMADOT II instructions + // Support smt.vmadot/smt.vmadotu/smt.vmadotus/smt.vmadotsu + foreach a = VTypeEncodes in + def VMADOT#!toupper(a.Name) : + SMTVMADotII<a.Encoding, "smt.vmadot"#a.Name>, Sched<[]>; + + // VMADOT Slide + foreach a = SlideEncodes in + foreach b = VTypeEncodes in + def VMADOT#!toupper(a.Name)#!toupper(b.Name): + SMTVMADotSlideII<a.Encoding, b.Encoding, "smt.vmadot"#a.Name#b.Name>, Sched<[]>; + + // Support smt.vmadot.sp/smt.vmadotu.sp/smt.vmadotus.sp/smt.vmadotsu.sp + foreach a = VTypeEncodes in + def VMADOT#!toupper(a.Name)#_SP : + SMTVMADOTSP<a.Encoding, "smt.vmadot"#a.Name#".sp", + "$vd, $vs1, $vs2, $vmask, $imm2$vtype">, Sched<[]>; + + // Support smt.vmadot.hp/smt.vmadotu.hp/smt.vmadotus.hp/smt.vmadotsu.hp + foreach c = HPEncodes in + def VMADOT#!toupper(c.Name)#_HP : + SMTVMADOTHP<c.Encoding, "smt.vmadot"#c.Name#".hp", + "$vd, $vs1, $vs2, $vmask, $imm3$vtype">, Sched<[]>; + + let DestEEW = EEWSEWx2, Constraints = "$vd = $vd_wb"in { + // VFWMADOT + def VFWMADOT : + SMTVFWMADOT<0b100, (outs VRM2:$vd_wb), + (ins VRM2:$vd, VR:$vs1, VR:$vs2, SMT_FP:$vtype), + "smt.vfwmadot", "$vd, $vs1, $vs2$vtype">, Sched<[]>; + // VFWMADOT Slide + def VFWMADOT1 : VFWMADTSLIDE_INSN<0b101, "smt.vfwmadot1">; + def VFWMADOT2 : VFWMADTSLIDE_INSN<0b110, "smt.vfwmadot2">; + def VFWMADOT3 : VFWMADTSLIDE_INSN<0b111, "smt.vfwmadot3">; + } + + def VNPACK_VV : VNPACK_INSN<0b0110001, 0b0, "smt.vnpack.vv">; + def VNSPACK_VV : VNPACK_INSN<0b0110001, 0b1, "smt.vnspack.vv">; + def VNPACK4_VV : VNPACK_INSN<0b0100001, 0b0, "smt.vnpack4.vv">; + def VNSPACK4_VV : VNPACK_INSN<0b0100001, 0b1, "smt.vnspack4.vv">; + def VPACK_VV : VPACK_INSN<0b0110011, 0b0, "smt.vpack.vv">; + def VUPACK_VV : VPACK_INSN<0b0110011, 0b1, "smt.vupack.vv">; + } + } } // DecoderNamespace = "XSMT" diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index d7869e12afb56..308846f407281 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -869,7 +869,8 @@ def SPACEMIT_A100 : RISCVProcessorModel<"spacemit-a100", FeatureStdExtZvksc, FeatureStdExtZvksg, FeatureStdExtZvl1024b, - FeatureUnalignedScalarMem]), + FeatureUnalignedScalarMem, + FeatureVendorXSMTVDotII]), [TuneDLenFactor2, TuneOptimizedNF2SegmentLoadStore, TuneOptimizedNF3SegmentLoadStore, diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 58af1f863f7bf..63734fbf1e288 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -866,8 +866,12 @@ def VR : VReg<!listconcat(VM1VTs, VMaskVTs), let DecoderMethod = "DecodeSimpleRegisterClass<RISCV::V0, 32>"; } +def VRV0V1 : VReg<!listconcat(VM1VTs, VMaskVTs), (add V0, V1), 1>; + def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs), (sub VR, V0), 1>; +def VRNoV0V1 : VReg<!listconcat(VM1VTs, VMaskVTs), (sub VR, V0, V1), 1>; + def VRM2 : VReg<VM2VTs, (add (sequence "V%uM2", 8, 31, 2), (sequence "V%uM2", 6, 0, 2)), 2> { let DecoderMethod = "DecodeVectorRegisterClass<RISCV::VRM2RegClassID, 32, 2>"; diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 92a514f932632..0e9e4e121fd6d 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -259,6 +259,7 @@ ; CHECK-NEXT: xsifivecdiscarddlone - 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction). ; CHECK-NEXT: xsifivecflushdlone - 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction). ; CHECK-NEXT: xsmtvdot - 'XSMTVDot' (SpacemiT Vector Dot Product Extension). +; CHECK-NEXT: xsmtvdotII - 'XSMTVDot' (SpacemiT Vector Dot Product 2.0 Extension). ; CHECK-NEXT: xtheadba - 'XTHeadBa' (T-Head address calculation instructions). ; CHECK-NEXT: xtheadbb - 'XTHeadBb' (T-Head basic bit-manipulation instructions). ; CHECK-NEXT: xtheadbs - 'XTHeadBs' (T-Head single-bit instructions). diff --git a/llvm/test/MC/RISCV/xsmtvdot-valid.s b/llvm/test/MC/RISCV/xsmtvdot-valid.s index 4f402236099d6..bde8a42403c1b 100644 --- a/llvm/test/MC/RISCV/xsmtvdot-valid.s +++ b/llvm/test/MC/RISCV/xsmtvdot-valid.s @@ -11,84 +11,84 @@ // CHECK-ENC: encoding: [0x2b,0x38,0x80,0xe2] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot v16, v0, v8 smt.vmadot v16, v0, v8 // CHECK-ENC: encoding: [0x2b,0x89,0x90,0xe2] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadotu v18, v1, v9 smt.vmadotu v18, v1, v9 // CHECK-ENC: encoding: [0x2b,0x2a,0xa1,0xe2] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadotsu v20, v2, v10 smt.vmadotsu v20, v2, v10 // CHECK-ENC: encoding: [0x2b,0x9b,0xb1,0xe2] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadotus v22, v3, v11 smt.vmadotus v22, v3, v11 // CHECK-ENC: encoding: [0x2b,0x3c,0xc8,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot1 v24, v16, v12 smt.vmadot1 v24, v16, v12 // CHECK-ENC: encoding: [0x2b,0x0d,0xd9,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot1u v26, v18, v13 smt.vmadot1u v26, v18, v13 // CHECK-ENC: encoding: [0x2b,0x2e,0xea,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot1su v28, v20, v14 smt.vmadot1su v28, v20, v14 // CHECK-ENC: encoding: [0x2b,0x1f,0xfb,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot1us v30, v22, v15 smt.vmadot1us v30, v22, v15 // CHECK-ENC: encoding: [0x2b,0x70,0x4c,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot2 v0, v24, v4 smt.vmadot2 v0, v24, v4 // CHECK-ENC: encoding: [0x2b,0x41,0x5d,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot2u v2, v26, v5 smt.vmadot2u v2, v26, v5 // CHECK-ENC: encoding: [0x2b,0x62,0x6e,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot2su v4, v28, v6 smt.vmadot2su v4, v28, v6 // CHECK-ENC: encoding: [0x2b,0x53,0x8f,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot2us v6, v30, v8 smt.vmadot2us v6, v30, v8 // CHECK-ENC: encoding: [0x2b,0xb1,0x80,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot3 v2, v0, v8 smt.vmadot3 v2, v0, v8 // CHECK-ENC: encoding: [0x2b,0x85,0x91,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot3u v10, v2, v9 smt.vmadot3u v10, v2, v9 // CHECK-ENC: encoding: [0x2b,0xa6,0xa2,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot3su v12, v4, v10 smt.vmadot3su v12, v4, v10 // CHECK-ENC: encoding: [0x2b,0x97,0xb3,0xe6] -// CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +// CHECK-ERROR: instruction requires the following: 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)){{$}} // CHECK-INST: smt.vmadot3us v14, v6, v11 smt.vmadot3us v14, v6, v11 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 9e7f23e2b4f76..111b0442e3b3c 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1364,6 +1364,7 @@ R"(All available -march extensions for RISC-V xsifivecdiscarddlone 1.0 xsifivecflushdlone 1.0 xsmtvdot 1.0 + xsmtvdotii 1.0 xtheadba 1.0 xtheadbb 1.0 xtheadbs 1.0 >From 0957d7572aeaf001c3d9b3447713720a2bb4f9dc Mon Sep 17 00:00:00 2001 From: wengliqin <[email protected]> Date: Thu, 11 Jun 2026 18:12:16 +0800 Subject: [PATCH 2/2] fix comments --- .../riscv-spacemit-a100.c | 1 + .../Driver/print-supported-extensions-riscv.c | 2 +- llvm/docs/RISCVUsage.rst | 4 +- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 6 +-- .../RISCV/Disassembler/RISCVDisassembler.cpp | 42 +++++++------------ .../RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 2 +- llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +- llvm/lib/Target/RISCV/RISCVInstrFormats.td | 1 - .../RISCV/RISCVInstrFormatsSpacemitV.td | 20 ++++----- llvm/test/CodeGen/RISCV/features-info.ll | 2 +- .../rvv/subregister-undef-early-clobber.mir | 16 +++---- 11 files changed, 42 insertions(+), 56 deletions(-) diff --git a/clang/test/Driver/print-enabled-extensions/riscv-spacemit-a100.c b/clang/test/Driver/print-enabled-extensions/riscv-spacemit-a100.c index 11fde408956bc..c56b476145a2a 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-spacemit-a100.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-spacemit-a100.c @@ -96,6 +96,7 @@ // CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation) // CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity) // CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types) +// CHECK-NEXT: xsmtvdotii 1.0 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 3ea2b846ee5d5..0e0849009542a 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -228,7 +228,7 @@ // CHECK-NEXT: xsifivecdiscarddlone 1.0 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction) // CHECK-NEXT: xsifivecflushdlone 1.0 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction) // CHECK-NEXT: xsmtvdot 1.0 'XSMTVDot' (SpacemiT Vector Dot Product Extension) -// CHECK-NEXT: xsmtvdotii 1.0 'XSMTVDotII' (SpacemiT Vector Dot Product 2.0 Extension) +// CHECK-NEXT: xsmtvdotii 1.0 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)) // CHECK-NEXT: xtheadba 1.0 'XTHeadBa' (T-Head address calculation instructions) // CHECK-NEXT: xtheadbb 1.0 'XTHeadBb' (T-Head basic bit-manipulation instructions) // CHECK-NEXT: xtheadbs 1.0 'XTHeadBs' (T-Head single-bit instructions) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 8d1ab1fa914b3..10bcdc8e251b7 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -573,11 +573,11 @@ The current vendor extensions supported are: ``XSMTVDot`` SpacemiT defines `Integrated Matrix Extension (IME) specification <https://github.com/spacemit-com/riscv-ime-extension-spec/releases/tag/v1.0>`__. - LLVM implement the hardware-adapted subset for SpacemiT X60, defined in the `feature document <https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1>`__ by SpacemiT. All instructions are prefixed with `smt.` as described in the implementation guide. Note that this implemented subset is `version 1.0.0 of the SpacemiT Vector Dot Product Extension specification`, which is strictly a subset of the full IME specification to reflect the capabilities of SpacemiT X60 hardware correctly. + LLVM implements the hardware-adapted subset for SpacemiT X60, defined in the `feature document <https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1>`__ by SpacemiT. All instructions are prefixed with `smt.` as described in the implementation guide. Note that this implemented subset is `version 1.0.0 of the SpacemiT Vector Dot Product Extension specification`, which is strictly a subset of the full IME specification to reflect the capabilities of SpacemiT X60 hardware correctly. ``XSMTVDotII`` SpacemiT defines `https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md`. - LLVM implement the hardware-adapted subset for SpacemiT A100 + LLVM implements the hardware-adapted subset for SpacemiT A100 Experimental C Intrinsics ========================= diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 5b603b7bb4482..ce64e69c3724a 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1139,7 +1139,7 @@ struct RISCVOperand final : public MCParsedAsmOperand { OS << '>'; break; case KindTy::SMTVType: - OS << "<smt: "; + OS << "<smtvtype: "; SMTVTypeModeToString(getSMTVType()); OS << '>'; break; @@ -2726,10 +2726,10 @@ ParseStatus RISCVAsmParser::parseSMTVType(OperandVector &Operands) { XSMTVTypeMode::SMTVTypeMode VType = XSMTVTypeMode::stringToSMTVTypeMode(Str); if (!isValidSMTVTypeMode(VType)) - return TokError("SpacemiT AI only support [i4|i8|bfp16|fp16] Mode"); + return TokError("SpacemiT AI only supports [i4|i8|bfp16|fp16] Mode"); // bfp16 and fp16 has the same encoding in SpacemiT AI - // In AsmParse, need conside bfp16 as fp16 + // In AsmParser, need to consider bfp16 as fp16 if (VType == XSMTVTypeMode::SMTVTypeMode::SMT_BFP16) { VType = XSMTVTypeMode::SMTVTypeMode::SMT_FP16; } diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index a6f71f12ae675..8b60626e15f04 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -217,34 +217,20 @@ static DecodeStatus DecodeVectorRegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } -static DecodeStatus DecodeVRV0V1RegisterClass(MCInst &Inst, uint32_t RegNo, - uint64_t Address, - const MCDisassembler *Decoder) { - if (RegNo >= 2) - return MCDisassembler::Fail; - - return DecodeSimpleRegisterClass<RISCV::V0, 2>(Inst, RegNo, Address, Decoder); -} - -static DecodeStatus DecodeVRNoV0V1RegisterClass(MCInst &Inst, uint32_t RegNo, - uint64_t Address, - const MCDisassembler *Decoder) { - if (RegNo == 0 || RegNo == 1) - return MCDisassembler::Fail; - - return DecodeSimpleRegisterClass<RISCV::V0, 32>(Inst, RegNo, Address, - Decoder); -} - -static DecodeStatus DecodeVRM2NoV0RegisterClass(MCInst &Inst, uint32_t RegNo, - uint64_t Address, - const MCDisassembler *Decoder) { - if (RegNo == 0) - return MCDisassembler::Fail; - - return DecodeVectorRegisterClass<RISCV::VRM2RegClassID, 32, 2>( - Inst, RegNo, Address, Decoder); -} +constexpr auto DecodeVRRegisterClass = DecodeSimpleRegisterClass<RISCV::V0, 32>; +constexpr auto DecodeVRM2RegisterClass = + DecodeVectorRegisterClass<RISCV::VRM2RegClassID, 32, 2>; + +constexpr bool PredV0V1Only(uint32_t RegNo) { return RegNo < 2; } +constexpr bool PredNoV0V1(uint32_t RegNo) { return RegNo >= 2; } +constexpr bool PredVM2NOV0(uint32_t RegNo) { return RegNo != 0; } + +constexpr auto DecodeVRV0V1RegisterClass = + DecodeFilteredRegisterClass<DecodeVRRegisterClass, PredV0V1Only>; +constexpr auto DecodeVRNoV0V1RegisterClass = + DecodeFilteredRegisterClass<DecodeVRRegisterClass, PredNoV0V1>; +constexpr auto DecodeVRM2NoV0RegisterClass = + DecodeFilteredRegisterClass<DecodeVRM2RegisterClass, PredVM2NOV0>; static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index 1e1be42540397..a6174310201d0 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -167,7 +167,7 @@ void RISCVInstPrinter::printSMTVType(const MCInst *MI, unsigned OpNo, auto VType = static_cast<XSMTVTypeMode::SMTVTypeMode>(MI->getOperand(OpNo).getImm()); assert(XSMTVTypeMode::isValidSMTVTypeMode(VType) && - "SpacemiT AI only support [i4|i8|fp16|bfp16] Mode"); + "SpacemiT AI only supports [i4|i8|fp16|bfp16] Mode"); O << ", " << XSMTVTypeMode::SMTVTypeModeToString(VType); } diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index d3fbd92dbf806..e976c6ef6be71 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1800,7 +1800,7 @@ def HasVendorXSMTVDot "'XSMTVDot' (SpacemiT Vector Dot Product Extension)">; def FeatureVendorXSMTVDotII - : RISCVExtension<1, 0, "SpacemiT Vector Dot Product 2.0 Extension", + : RISCVExtension<1, 0, "SpacemiT Vector Extension for Matrix(2.0)", [FeatureStdExtZve32f]>; def HasVendorXSMTVDotII : Predicate<"Subtarget->hasVendorXSMTVDotII()">, diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td index d48de5cc0f394..e3c93dc93a686 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -58,7 +58,6 @@ def InstFormatQC_EB : InstFormat<24>; def InstFormatQC_EJ : InstFormat<25>; def InstFormatQC_ES : InstFormat<26>; def InstFormatNDS_BRANCH_10 : InstFormat<27>; -def InstFormatSMT : InstFormat<28>; def InstFormatOther : InstFormat<31>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td index aa3e515a8a464..59e6dccaa6f67 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsSpacemitV.td @@ -94,7 +94,7 @@ def SMTI8 : AsmOperandClass { let Name = "SMTI8"; let RenderMethod = "addSMTVTypeOperand"; let DiagnosticType = "InvalidSMTI8"; - let DiagnosticString = "smt.vmadot with slide only support i8 type"; + let DiagnosticString = "smt.vmadot with slide only supports i8 type"; let ParserMethod = "parseSMTVType"; let IsOptional = 1; let DefaultMethod = "defaultSMTVType"; @@ -116,7 +116,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { // Base vector dot product (no slide) format. class SMTVMADot<bits<2> sign, string opcodestr, bit EarlyClobber = 0> : RVInst<(outs VRM2:$vd_wb), (ins VRM2:$vd, VR:$vs1, VR:$vs2), - opcodestr, "$vd, $vs1, $vs2", [], InstFormatSMT> { + opcodestr, "$vd, $vs1, $vs2", [], InstFormatR> { bits<5> vd; bits<5> vs1; bits<5> vs2; @@ -137,7 +137,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class SMTVMADotSlide<bits<2> funct2, bits<2> sign, string opcodestr, bit EarlyClobber = 0> : RVInst<(outs VRM2:$vd_wb), (ins VRM2:$vd, VRM2:$vs1, VR:$vs2), - opcodestr, "$vd, $vs1, $vs2", [], InstFormatSMT> { + opcodestr, "$vd, $vs1, $vs2", [], InstFormatR> { bits<5> vd; bits<5> vs1; bits<5> vs2; @@ -157,7 +157,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class SMTVMADotII<bits<2> sign, string opcodestr, bit EarlyClobber = 0> : RVInst<(outs VRM2:$vd_wb), (ins VRM2:$vd, VR:$vs1, VR:$vs2, SMT_INT:$vtype), opcodestr, - "$vd, $vs1, $vs2$vtype", [], InstFormatSMT> { + "$vd, $vs1, $vs2$vtype", [], InstFormatR> { bits<5> vd; bits<5> vs1; bits<5> vs2; @@ -177,13 +177,13 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { let UseNamedOperandTable = true; } - // Now only support element type i8 for sliding-window dot-product + // Currently only i8 element type is supported for sliding-window dot-product // instructions class SMTVMADotSlideII<bits<2> slide, bits<2> sign, string opcodestr, bit EarlyClobber = 0> : RVInst<(outs VRM2:$vd_wb), (ins VRM2:$vd, VRM2:$vs1, VR:$vs2, SMT_I8:$vtype), opcodestr, - "$vd, $vs1, $vs2$vtype", [], InstFormatSMT> { + "$vd, $vs1, $vs2$vtype", [], InstFormatR> { bits<5> vd; bits<5> vs1; bits<5> vs2; @@ -208,7 +208,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { : RVInst<(outs VRM2NoV0:$vd_wb), (ins VRM2NoV0:$vd, VRM2NoV0:$vs1, VRNoV0V1:$vs2, VRV0V1:$vmask, uimm2:$imm2, SMT_INT:$vtype), - opcodestr, argstr, [], InstFormatSMT> { + opcodestr, argstr, [], InstFormatR> { bits<5> vd; bits<5> vs1; bits<5> vs2; @@ -238,7 +238,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { : RVInst<(outs VRNoV0V1:$vd_wb), (ins VRNoV0V1:$vd, VRNoV0V1:$vs1, VRNoV0V1:$vs2, VRV0V1:$vmask, uimm3:$imm3, SMT_INT:$vtype), - opcodestr, argstr, [], InstFormatSMT> { + opcodestr, argstr, [], InstFormatR> { bits<5> vd; bits<5> vs1; bits<5> vs2; @@ -262,7 +262,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class SMTVFWMADOT<bits<3> funct3, dag outs, dag ins, string opcodestr, string argstr> - : RVInst<outs, ins, opcodestr, argstr, [], InstFormatSMT> { + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { bits<5> vd; bits<5> vs1; bits<5> vs2; @@ -281,7 +281,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { class SMTVPACK<bits<7> funct7, bit funct1, dag outs, dag ins, string opcodestr, string argstr> - : RVInst<outs, ins, opcodestr, argstr, [], InstFormatSMT> { + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> { bits<5> vd; bits<5> vs1; bits<5> vs2; diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 0e9e4e121fd6d..a6d519032f6df 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -259,7 +259,7 @@ ; CHECK-NEXT: xsifivecdiscarddlone - 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction). ; CHECK-NEXT: xsifivecflushdlone - 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction). ; CHECK-NEXT: xsmtvdot - 'XSMTVDot' (SpacemiT Vector Dot Product Extension). -; CHECK-NEXT: xsmtvdotII - 'XSMTVDot' (SpacemiT Vector Dot Product 2.0 Extension). +; CHECK-NEXT: xsmtvdotii - 'XSMTVDotII' (SpacemiT Vector Extension for Matrix(2.0)). ; CHECK-NEXT: xtheadba - 'XTHeadBa' (T-Head address calculation instructions). ; CHECK-NEXT: xtheadbb - 'XTHeadBb' (T-Head basic bit-manipulation instructions). ; CHECK-NEXT: xtheadbs - 'XTHeadBs' (T-Head single-bit instructions). diff --git a/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir index 559dc12be3a3d..3e87d73544fa4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir +++ b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir @@ -93,7 +93,7 @@ body: | ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_0 - ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrnov0v1 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_3 ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 @@ -131,7 +131,7 @@ body: | ; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: [[INIT_UNDEF:%[0-9]+]]:vrm2 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm2_0 - ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrnov0v1 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm1_2 ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed [[INSERT_SUBREG2]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 @@ -324,7 +324,7 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_0 - ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0v1 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_3 ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 @@ -364,7 +364,7 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_0 - ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0v1 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_2 ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 @@ -404,7 +404,7 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_3 - ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0v1 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_5 ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 @@ -444,7 +444,7 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_3 - ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0v1 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_4 ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 @@ -484,7 +484,7 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_2 - ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0v1 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_7 ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 @@ -524,7 +524,7 @@ body: | ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[INIT_UNDEF]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INIT_UNDEF1:%[0-9]+]]:vrm2nov0 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[INIT_UNDEF1]], %subreg.sub_vrm2_2 - ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:zzz_vrmf8nov0 = INIT_UNDEF + ; CHECK-NEXT: [[INIT_UNDEF2:%[0-9]+]]:vrnov0v1 = INIT_UNDEF ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[INIT_UNDEF2]], %subreg.sub_vrm1_6 ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed [[INSERT_SUBREG3]], 0, 0 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
