================
@@ -1430,6 +1430,40 @@ mlir::LogicalResult
CIRToLLVMCastOpLowering::matchAndRewrite(
return mlir::success();
}
+mlir::LogicalResult CIRToLLVMBuiltinIntCastOpLowering::matchAndRewrite(
+ cir::BuiltinIntCastOp op, OpAdaptor adaptor,
+ mlir::ConversionPatternRewriter &rewriter) const {
+ // Both the CIR integer and the builtin integer/index lower to LLVM integer
+ // types, so this cast becomes an integer resize. Signedness is taken from
+ // the CIR integer side (the builtin/index side is treated as signless).
+ bool isUnsigned = true;
+ if (auto cirSrc = mlir::dyn_cast<cir::IntType>(op.getSrc().getType()))
+ isUnsigned = cirSrc.isUnsigned();
+ else if (auto cirDst = mlir::dyn_cast<cir::IntType>(op.getType()))
+ isUnsigned = cirDst.isUnsigned();
+
+ mlir::Value llvmSrc = adaptor.getSrc();
+ mlir::Type llvmDstTy = getTypeConverter()->convertType(op.getType());
+ auto srcIntTy = mlir::cast<mlir::IntegerType>(llvmSrc.getType());
+ auto dstIntTy = mlir::cast<mlir::IntegerType>(llvmDstTy);
+ unsigned srcWidth = srcIntTy.getWidth();
+ unsigned dstWidth = dstIntTy.getWidth();
+
+ // Fixed-width builtin integers must match the CIR integer wdith.
----------------
erichkeane wrote:
```suggestion
// Fixed-width builtin integers must match the CIR integer width.
```
https://github.com/llvm/llvm-project/pull/201592
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
