https://github.com/yxsamliu updated https://github.com/llvm/llvm-project/pull/206350
>From 8e2f2be876d830de888d747438bf480cf6a9c977 Mon Sep 17 00:00:00 2001 From: "Yaxun (Sam) Liu" <[email protected]> Date: Fri, 26 Jun 2026 13:29:24 -0400 Subject: [PATCH] [HIP] Remove redundant device optimization pipeline The new offload driver uses the linker wrapper for HIP device codegen. In default non-RDC mode, the wrapper uses the non-LTO path (`--no-lto`) and compiles device bitcode to ISA through the normal optimization pipeline. Do not run the LLVM optimizer in the earlier HIP device cc1 job when it only produces intermediate bitcode for this default non-RDC path. This avoids a non-parallel redundant optimization pipeline and reduces compile time. Keep the optimizer for RDC and explicit offload LTO, where the LTO flow expects optimized input bitcode. Also keep it when the user requests final LLVM output with `-emit-llvm`, so the requested optimization level is honored. --- clang/lib/Driver/ToolChains/Clang.cpp | 21 +++++++++ .../hip-new-driver-disable-llvm-passes.hip | 43 +++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 clang/test/Driver/hip-new-driver-disable-llvm-passes.hip diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index bb3fbc3c585a6..6334e5333d2a6 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -5428,6 +5428,27 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, CmdArgs.push_back("-flto-unit"); } } + + // Default non-RDC HIP uses the linker wrapper's non-LTO compile path for + // device bitcode. Skip the early cc1 optimizer so the overall flow has one + // classic optimization pipeline. Keep optimized bitcode for explicit LTO, + // RDC, and final -emit-llvm output. + bool HIPUsesDefaultNonRDCNonLTO = + IsHIPDevice && !IsRDCMode && + !Args.hasArg(options::OPT_foffload_lto_EQ, + options::OPT_fno_offload_lto) && + !Args.hasArg(options::OPT_fprofile_generate, + options::OPT_fprofile_generate_EQ, + options::OPT_fprofile_instr_generate, + options::OPT_fprofile_instr_generate_EQ) && + !Triple.isSPIRV(); + if ((JA.getType() == types::TY_LLVM_BC || + JA.getType() == types::TY_LTO_BC) && + HIPUsesDefaultNonRDCNonLTO && !Args.hasArg(options::OPT_emit_llvm) && + Args.hasFlag(options::OPT_offload_new_driver, + options::OPT_no_offload_new_driver, + C.getActiveOffloadKinds() != Action::OFK_None)) + CmdArgs.push_back("-disable-llvm-passes"); } Args.AddLastArg(CmdArgs, options::OPT_dumpdir); diff --git a/clang/test/Driver/hip-new-driver-disable-llvm-passes.hip b/clang/test/Driver/hip-new-driver-disable-llvm-passes.hip new file mode 100644 index 0000000000000..776c6ab837d8c --- /dev/null +++ b/clang/test/Driver/hip-new-driver-disable-llvm-passes.hip @@ -0,0 +1,43 @@ +// RUN: %clang -### --target=x86_64-linux-gnu \ +// RUN: --offload-arch=gfx90a -nogpuinc -nogpulib \ +// RUN: -O3 -c -x hip %s 2>&1 | FileCheck -check-prefix=DEFAULT %s +// RUN: %clang -### --target=x86_64-linux-gnu \ +// RUN: --offload-arch=gfx90a -nogpuinc -nogpulib -fgpu-rdc \ +// RUN: -O3 -c -x hip %s 2>&1 | FileCheck -check-prefix=RDC %s +// RUN: %clang -### --target=x86_64-linux-gnu \ +// RUN: --offload-arch=gfx90a -nogpuinc -nogpulib -foffload-lto \ +// RUN: -O3 -c -x hip %s 2>&1 | FileCheck -check-prefix=LTO %s +// RUN: %clang -### --target=x86_64-linux-gnu \ +// RUN: --offload-arch=gfx90a -nogpuinc -nogpulib \ +// RUN: -O3 --cuda-device-only -emit-llvm -c -x hip %s 2>&1 \ +// RUN: | FileCheck -check-prefix=USER-BC %s +// RUN: %clang -### --target=x86_64-linux-gnu \ +// RUN: --offload-arch=gfx90a -nogpuinc -nogpulib \ +// RUN: -O3 --cuda-device-only -emit-llvm -S -x hip %s 2>&1 \ +// RUN: | FileCheck -check-prefix=USER-IR %s + +// DEFAULT: "-cc1" "-triple" "amdgcn-amd-amdhsa" +// DEFAULT-SAME: "-emit-llvm-bc" +// DEFAULT-SAME: "-disable-llvm-passes" +// DEFAULT: "{{.*}}llvm-offload-binary" +// DEFAULT: "{{.*}}clang-linker-wrapper" +// DEFAULT-SAME: "--no-lto" + +// RDC: "-cc1" "-triple" "amdgcn-amd-amdhsa" +// RDC-SAME: "-emit-llvm-bc" +// RDC-SAME: "-flto=full" +// RDC-NOT: "-disable-llvm-passes" + +// LTO: "-cc1" "-triple" "amdgcn-amd-amdhsa" +// LTO-SAME: "-emit-llvm-bc" +// LTO-SAME: "-flto=full" +// LTO-NOT: "-disable-llvm-passes" +// LTO: "{{.*}}clang-linker-wrapper" + +// USER-BC: "-cc1" "-triple" "amdgcn-amd-amdhsa" +// USER-BC-SAME: "-emit-llvm-bc" +// USER-BC-NOT: "-disable-llvm-passes" + +// USER-IR: "-cc1" "-triple" "amdgcn-amd-amdhsa" +// USER-IR-SAME: "-emit-llvm" +// USER-IR-NOT: "-disable-llvm-passes" _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
