[clang] [CIR][AArc64] Add lowering for fp16 intrinsics (step + rounding) (PR #207511)

[Jiahao Guo via cfe-commits]

================
@@ -2906,24 +2914,72 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned 
builtinID, const CallExpr *expr,
     return emitNeonCall(cgm, builder, {argTy, sInt32Ty}, ops, intrName, ty,
                         loc);
   }
-  case NEON::BI__builtin_neon_vrndah_f16:
+  case NEON::BI__builtin_neon_vrndah_f16: {
----------------
E00N777 wrote:

Maybe we could use `emitCallMaybeConstrainedBuiltin` in this and other places

https://github.com/llvm/llvm-project/pull/207511
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