================
@@ -0,0 +1,76 @@
+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown
-target-feature +acev1 \
+// RUN: -target-feature +avx512f -emit-llvm -o - -Wall -Werror -pedantic |
FileCheck %s
+
+// Tests inline assembly with ACE v1 tile registers
+
+#include <immintrin.h>
+
+void test_acev1_inline_asm_outer_product(void) {
+ // CHECK-LABEL: @test_acev1_inline_asm_outer_product
+ // CHECK: call void asm sideeffect "tilezero %tmm0
+ // CHECK: top4buud %zmm0, %zmm1, %tmm0
+ // CHECK: tilestored %tmm0
+ __asm__ volatile (
+ "tilezero %%tmm0 \n\t"
+ "top4buud %%zmm0, %%zmm1, %%tmm0 \n\t"
+ "tilestored %%tmm0, 0(%%rdi) \n\t"
+ ::: "memory", "tmm0", "zmm0", "zmm1"
----------------
mahesh-attarde wrote:
This is interesting complex use case as well.
```
#define SRCDEST 7
__m512 q;
asm volatile("tilemovrow %%eax, %0, %%tmm%c1" : : "v"(q),"i" (SRCDEST));
```
https://github.com/llvm/llvm-project/pull/208408
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