================
@@ -3858,6 +3858,56 @@ bool X86AsmParser::parseInstruction(ParseInstructionInfo
&Info, StringRef Name,
}
}
+ // ACE BSR instructions: Strip %bsr0 operands and distinguish load/store.
+ // BSR (Block Scale Register) is implicit in the encoding (always BSR0),
+ // but the spec requires explicit %bsr0 in assembly syntax for
disambiguation.
+ //
+ // For BSRMOVH and BSRMOVL, load vs store is determined by operand order:
+ // - ATT load: zmm/mem, bsr0 (ZMM first, BSR last) - move TO bsr0
+ // - ATT store: bsr0, zmm/mem (BSR first, ZMM last) - move FROM bsr0
+ // - Intel syntax reverses source/dest from ATT
+ //
+ // Note: Check for specific ACE BSR instructions to avoid matching standard
+ // x86 "bsrl"/"bsrq" (bit scan reverse).
----------------
mahesh-attarde wrote:
Why did we get into manual handling?
https://github.com/llvm/llvm-project/pull/208408
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
