================ @@ -0,0 +1,417 @@ +//===---- X86InstrACE.td - ACE Instruction Set Extension --*- tablegen -*--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the ACE (AI Compute +// Extensions) instruction set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// ACE instructions + +let Predicates = [HasACEV1, In64BitMode] in { + +// BSRINIT - Initialize Block Scale Register +// VEX.128.F2.0F38.W1 49 11:000:000 - BSRINIT bsr0 +// BSR is implicit destination, ModRM = 11:000:000 (mod=11, reg=000, r/m=000) +// Note: BSR0 is implicit (via Defs), not in operand list. Asm syntax has no explicit operand. +let SchedRW = [WriteSystem], hasSideEffects = 1, Defs = [BSR0] in { + def BSRINIT : I<0x49, MRM_C0, (outs), (ins), + "bsrinit", []>, ---------------- mahesh-attarde wrote:
In spec, BSRINIT takes argument $BSR0. but here we did not add it ins, printing assembly we are forcing bsr print. https://github.com/llvm/llvm-project/pull/208408 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
