https://github.com/chrisnc created https://github.com/llvm/llvm-project/pull/213588
Update the expected codegen as-needed. >From 5c7ff6f0cdea083dd7e219cf1feed1282162a5f5 Mon Sep 17 00:00:00 2001 From: Chris Copeland <[email protected]> Date: Sun, 2 Aug 2026 17:42:35 -0700 Subject: [PATCH] [ARM] Fix invalid target triples in tests Update the expected codegen as-needed. --- clang/test/CodeGenCXX/bitfield-layout.cpp | 2 +- clang/test/Frontend/darwin-eabi.c | 2 +- lld/test/ELF/arm-thunk-reuse.s | 2 +- .../CostModel/ARM/muls-in-smlal-patterns.ll | 4 +- .../CostModel/ARM/muls-in-umull-patterns.ll | 4 +- llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll | 2 +- llvm/test/CodeGen/ARM/analyze-branch-bkpt.ll | 2 +- llvm/test/CodeGen/ARM/cls.ll | 78 ++++--------------- llvm/test/CodeGen/ARM/fp16-fusedMAC.ll | 24 +++--- llvm/test/CodeGen/ARM/half.ll | 8 +- .../CodeGen/ARM/interrupt-save-fp-attr.ll | 4 +- llvm/test/CodeGen/ARM/loop-align-cortex-m.ll | 2 +- .../CodeGen/ARM/minnum-maxnum-intrinsics.ll | 9 ++- llvm/test/CodeGen/ARM/useaa.ll | 2 +- .../LowOverheadLoops/lsr-profitable-chain.ll | 2 +- .../CodeGen/Thumb2/aligned-nonfallthrough.ll | 2 +- .../inlineasm-error-t-toofewregs-mve.ll | 2 +- llvm/test/CodeGen/Thumb2/inlineasm-mve.ll | 18 ++--- .../Thumb2/unreachable-large-offset-gep.ll | 2 +- llvm/test/MC/ARM/ras-extension.s | 2 +- .../Disassembler/ARM/ras-extension-thumb.txt | 2 +- .../CodeGenPrepare/ARM/memory-intrinsics.ll | 2 +- .../ARM/vctp-chains-inseltpoison.ll | 2 +- .../LoopStrengthReduce/ARM/vctp-chains.ll | 2 +- llvm/test/tools/llvm-mca/ARM/m4-int.s | 2 +- llvm/test/tools/llvm-mca/ARM/m55-fp.s | 2 +- llvm/test/tools/llvm-mca/ARM/m55-int.s | 2 +- llvm/test/tools/llvm-mca/ARM/m55-mve-fp.s | 2 +- llvm/test/tools/llvm-mca/ARM/m55-mve-int.s | 2 +- llvm/test/tools/llvm-mca/ARM/m55-mve-ldst.s | 2 +- llvm/test/tools/llvm-mca/ARM/m55-mve-pred.s | 2 +- llvm/test/tools/llvm-mca/ARM/m55-storefwd.s | 2 +- llvm/test/tools/llvm-mca/ARM/m7-fp.s | 2 +- llvm/test/tools/llvm-mca/ARM/m7-int.s | 2 +- llvm/test/tools/llvm-mca/ARM/m85-fp.s | 2 +- llvm/test/tools/llvm-mca/ARM/m85-int.s | 2 +- llvm/test/tools/llvm-mca/ARM/m85-mve-fp.s | 2 +- llvm/test/tools/llvm-mca/ARM/m85-mve-int.s | 2 +- llvm/test/tools/llvm-mca/ARM/m85-mve-pred.s | 2 +- 39 files changed, 81 insertions(+), 130 deletions(-) diff --git a/clang/test/CodeGenCXX/bitfield-layout.cpp b/clang/test/CodeGenCXX/bitfield-layout.cpp index 66a140a966c64..c485dee980ed8 100644 --- a/clang/test/CodeGenCXX/bitfield-layout.cpp +++ b/clang/test/CodeGenCXX/bitfield-layout.cpp @@ -1,7 +1,7 @@ // RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -emit-llvm -o - -O3 | FileCheck -check-prefix=CHECK -check-prefix=CHECK-LP64 %s // RUN: %clang_cc1 %s -triple=i386-apple-darwin10 -emit-llvm -o - -O3 | FileCheck %s // RUN: %clang_cc1 %s -triple=aarch64_be -emit-llvm -o - -O3 | FileCheck %s -// RUN: %clang_cc1 %s -triple=thumbv7_be-none-eabi -emit-llvm -o - -O3 | FileCheck %s +// RUN: %clang_cc1 %s -triple=thumbebv7-none-eabi -emit-llvm -o - -O3 | FileCheck %s // RUN: %clang_cc1 %s -triple=x86_64-unknown-unknown -emit-llvm -o - -O3 -std=c++11 | FileCheck -check-prefix=CHECK -check-prefix=CHECK-LP64 %s // CHECK-LP64: %union.Test1 = type { i32, [4 x i8] } diff --git a/clang/test/Frontend/darwin-eabi.c b/clang/test/Frontend/darwin-eabi.c index b94bf26e2853f..6340a01e5f5e5 100644 --- a/clang/test/Frontend/darwin-eabi.c +++ b/clang/test/Frontend/darwin-eabi.c @@ -5,7 +5,7 @@ // RUN: %clang --target=armv8m.main-apple-darwin -dM -E %s | FileCheck %s // RUN: %clang --target=armv8.1m.main-apple-darwin -dM -E %s | FileCheck %s // RUN: %clang_cc1 -triple thumbv7m-apple-unknown-macho -dM -E %s | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8m-apple-unknown-macho -dM -E %s | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8m.main-apple-unknown-macho -dM -E %s | FileCheck %s // CHECK-NOT: __ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__ // CHECK-NOT: __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ diff --git a/lld/test/ELF/arm-thunk-reuse.s b/lld/test/ELF/arm-thunk-reuse.s index f6815da7af496..cde68169144ab 100644 --- a/lld/test/ELF/arm-thunk-reuse.s +++ b/lld/test/ELF/arm-thunk-reuse.s @@ -1,6 +1,6 @@ # REQUIRES: arm # RUN: rm -rf %t && split-file %s %t -# RUN: llvm-mc -filetype=obj -triple=armv7-a-none-eabi --arm-add-build-attributes %t/a.s -o %t/a.o +# RUN: llvm-mc -filetype=obj -triple=armv7a-none-eabi --arm-add-build-attributes %t/a.s -o %t/a.o # RUN: ld.lld -pie -T %t/lds %t/a.o -o %t/a # RUN: llvm-objdump --no-print-imm-hex -d --no-show-raw-insn %t/a | FileCheck %s # RUN: llvm-objdump -s --triple=armv7a-none-linux-gnueabi %t/a | FileCheck --check-prefix=CHECK-LE %s diff --git a/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll b/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll index 3ae02cdec5aba..cdb730929fe37 100644 --- a/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll +++ b/llvm/test/Analysis/CostModel/ARM/muls-in-smlal-patterns.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main -mattr=+dsp < %s | FileCheck %s -; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1m.main -mattr=+dsp < %s | FileCheck %s +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP define i64 @test(i16 %a, i16 %b) { ; CHECK-LABEL: 'test' diff --git a/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll b/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll index 04a952098a9c6..b904a6f9d9def 100644 --- a/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll +++ b/llvm/test/Analysis/CostModel/ARM/muls-in-umull-patterns.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5 -; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main -mattr=+dsp < %s | FileCheck %s -; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1-m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1m.main -mattr=+dsp < %s | FileCheck %s +; RUN: opt -passes="print<cost-model>" -cost-kind=all 2>&1 -disable-output -mtriple thumbv8.1m.main < %s | FileCheck %s --check-prefix=CHECK-NO-DSP define i64 @test(i16 %a, i16 %b) { ; CHECK-LABEL: 'test' diff --git a/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll b/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll index 5a5025d94b4da..270d848e867c8 100644 --- a/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll +++ b/llvm/test/CodeGen/ARM/ParallelDSP/squaring.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=armv8-a-linux-gnueabihf -arm-parallel-dsp -dce --verify %s -S -o - | FileCheck %s +; RUN: opt -mtriple=armv8a-linux-gnueabihf -arm-parallel-dsp -dce --verify %s -S -o - | FileCheck %s define dso_local void @a() align 2 { ; CHECK-LABEL: @a( diff --git a/llvm/test/CodeGen/ARM/analyze-branch-bkpt.ll b/llvm/test/CodeGen/ARM/analyze-branch-bkpt.ll index d6a2f58589c32..6cd164f2689b6 100644 --- a/llvm/test/CodeGen/ARM/analyze-branch-bkpt.ll +++ b/llvm/test/CodeGen/ARM/analyze-branch-bkpt.ll @@ -1,4 +1,4 @@ -; RUN: llc -o - %s -mtriple thumbv4-unknown-linux-android | FileCheck --check-prefix=V4 %s +; RUN: llc -o - %s -mtriple thumbv4t-unknown-linux-android | FileCheck --check-prefix=V4 %s ; RUN: llc -o - %s -mtriple thumbv5-unknown-linux-android | FileCheck --check-prefix=V5 %s ; V4: udf #254 diff --git a/llvm/test/CodeGen/ARM/cls.ll b/llvm/test/CodeGen/ARM/cls.ll index 76d787e039ed2..9cbaa55d08622 100644 --- a/llvm/test/CodeGen/ARM/cls.ll +++ b/llvm/test/CodeGen/ARM/cls.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc -mtriple=armv5 %s -o - | FileCheck %s --check-prefixes=CHECKV5 -; RUN: llc -mtriple=thumbv8.1-m.main %s -o - | FileCheck %s --check-prefix=CHECKV8 +; RUN: llc -mtriple=thumbv8.1m.main %s -o - | FileCheck %s --check-prefix=CHECKV8 define i32 @cls(i32 %t) { ; CHECKV5-LABEL: cls: @@ -13,15 +13,11 @@ define i32 @cls(i32 %t) { ; ; CHECKV8-LABEL: cls: ; CHECKV8: @ %bb.0: -; CHECKV8-NEXT: push {r7, lr} -; CHECKV8-NEXT: asrs r1, r0, #31 -; CHECKV8-NEXT: eors r1, r0 -; CHECKV8-NEXT: lsls r0, r1, #1 -; CHECKV8-NEXT: adds r0, r0, #1 -; CHECKV8-NEXT: bl __clzsi2 -; CHECKV8-NEXT: pop {r7} -; CHECKV8-NEXT: pop {r1} -; CHECKV8-NEXT: bx r1 +; CHECKV8-NEXT: eor.w r0, r0, r0, asr #31 +; CHECKV8-NEXT: lsls r0, r0, #1 +; CHECKV8-NEXT: adds r0, #1 +; CHECKV8-NEXT: clz r0, r0 +; CHECKV8-NEXT: bx lr %cls.i = call i32 @llvm.arm.cls(i32 %t) ret i32 %cls.i } @@ -42,63 +38,17 @@ define i32 @cls64(i64 %t) { ; ; CHECKV8-LABEL: cls64: ; CHECKV8: @ %bb.0: -; CHECKV8-NEXT: push {r4, lr} -; CHECKV8-NEXT: movs r4, r0 ; CHECKV8-NEXT: cmp r1, #0 -; CHECKV8-NEXT: bpl .LBB1_2 -; CHECKV8-NEXT: @ %bb.1: -; CHECKV8-NEXT: mvns r4, r4 -; CHECKV8-NEXT: .LBB1_2: -; CHECKV8-NEXT: asrs r0, r1, #31 -; CHECKV8-NEXT: eors r0, r1 +; CHECKV8-NEXT: cinv r0, r0, mi +; CHECKV8-NEXT: clz r2, r0 +; CHECKV8-NEXT: eor.w r0, r1, r1, asr #31 ; CHECKV8-NEXT: lsls r0, r0, #1 -; CHECKV8-NEXT: adds r0, r0, #1 -; CHECKV8-NEXT: bl __clzsi2 +; CHECKV8-NEXT: adds r0, #1 +; CHECKV8-NEXT: clz r0, r0 ; CHECKV8-NEXT: cmp r0, #31 -; CHECKV8-NEXT: bne .LBB1_4 -; CHECKV8-NEXT: @ %bb.3: -; CHECKV8-NEXT: lsrs r0, r4, #1 -; CHECKV8-NEXT: orrs r0, r4 -; CHECKV8-NEXT: lsrs r1, r0, #2 -; CHECKV8-NEXT: orrs r1, r0 -; CHECKV8-NEXT: lsrs r0, r1, #4 -; CHECKV8-NEXT: orrs r0, r1 -; CHECKV8-NEXT: lsrs r1, r0, #8 -; CHECKV8-NEXT: orrs r1, r0 -; CHECKV8-NEXT: lsrs r0, r1, #16 -; CHECKV8-NEXT: orrs r0, r1 -; CHECKV8-NEXT: mvns r0, r0 -; CHECKV8-NEXT: lsrs r1, r0, #1 -; CHECKV8-NEXT: ldr r2, .LCPI1_0 -; CHECKV8-NEXT: ands r2, r1 -; CHECKV8-NEXT: subs r0, r0, r2 -; CHECKV8-NEXT: ldr r1, .LCPI1_1 -; CHECKV8-NEXT: lsrs r2, r0, #2 -; CHECKV8-NEXT: ands r0, r1 -; CHECKV8-NEXT: ands r2, r1 -; CHECKV8-NEXT: adds r0, r0, r2 -; CHECKV8-NEXT: lsrs r1, r0, #4 -; CHECKV8-NEXT: adds r0, r0, r1 -; CHECKV8-NEXT: ldr r1, .LCPI1_2 -; CHECKV8-NEXT: ands r1, r0 -; CHECKV8-NEXT: ldr r0, .LCPI1_3 -; CHECKV8-NEXT: muls r0, r1, r0 -; CHECKV8-NEXT: lsrs r0, r0, #24 -; CHECKV8-NEXT: adds r0, #31 -; CHECKV8-NEXT: .LBB1_4: -; CHECKV8-NEXT: pop {r4} -; CHECKV8-NEXT: pop {r1} -; CHECKV8-NEXT: bx r1 -; CHECKV8-NEXT: .p2align 2 -; CHECKV8-NEXT: @ %bb.5: -; CHECKV8-NEXT: .LCPI1_0: -; CHECKV8-NEXT: .long 1431655765 @ 0x55555555 -; CHECKV8-NEXT: .LCPI1_1: -; CHECKV8-NEXT: .long 858993459 @ 0x33333333 -; CHECKV8-NEXT: .LCPI1_2: -; CHECKV8-NEXT: .long 252645135 @ 0xf0f0f0f -; CHECKV8-NEXT: .LCPI1_3: -; CHECKV8-NEXT: .long 16843009 @ 0x1010101 +; CHECKV8-NEXT: it eq +; CHECKV8-NEXT: addeq.w r0, r2, #31 +; CHECKV8-NEXT: bx lr %cls.i = call i32 @llvm.arm.cls64(i64 %t) ret i32 %cls.i } diff --git a/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll b/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll index 6f1f40729bd60..f354553f02c15 100644 --- a/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll +++ b/llvm/test/CodeGen/ARM/fp16-fusedMAC.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=thumbv8.1-m-none-eabi -mattr=+fullfp16 -fp-contract=fast | FileCheck %s -; RUN: llc < %s -mtriple=thumbv8.1-m-none-eabi -mattr=+fullfp16,+slowfpvfmx -fp-contract=fast | FileCheck %s -check-prefix=DONT-FUSE +; RUN: llc < %s -mtriple=thumbv8.1m.main-none-eabi -mattr=+fullfp16 -fp-contract=fast | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8.1m.main-none-eabi -mattr=+fullfp16,+slowfpvfmx -fp-contract=fast | FileCheck %s -check-prefix=DONT-FUSE ; Check generated fp16 fused MAC and MLS. @@ -203,20 +203,20 @@ define arm_aapcs_vfpcc void @test_fma_const_fold(ptr %aa, ptr %bb) nounwind { define arm_aapcs_vfpcc void @test_fma_canonicalize(ptr %aa, ptr %bb) nounwind { ; CHECK-LABEL: test_fma_canonicalize: ; CHECK: @ %bb.0: -; CHECK-NEXT: vldr.16 s0, [r0] -; CHECK-NEXT: vldr.16 s2, [r1] -; CHECK-NEXT: vmov.f16 s4, #2.000000e+00 -; CHECK-NEXT: vfma.f16 s2, s0, s4 -; CHECK-NEXT: vstr.16 s2, [r0] +; CHECK-NEXT: vldr.16 s2, [r0] +; CHECK-NEXT: vldr.16 s4, [r1] +; CHECK-NEXT: vmov.f16 s0, #2.000000e+00 +; CHECK-NEXT: vfma.f16 s4, s2, s0 +; CHECK-NEXT: vstr.16 s4, [r0] ; CHECK-NEXT: bx lr ; ; DONT-FUSE-LABEL: test_fma_canonicalize: ; DONT-FUSE: @ %bb.0: -; DONT-FUSE-NEXT: vldr.16 s0, [r0] -; DONT-FUSE-NEXT: vldr.16 s2, [r1] -; DONT-FUSE-NEXT: vmov.f16 s4, #2.000000e+00 -; DONT-FUSE-NEXT: vfma.f16 s2, s0, s4 -; DONT-FUSE-NEXT: vstr.16 s2, [r0] +; DONT-FUSE-NEXT: vldr.16 s2, [r0] +; DONT-FUSE-NEXT: vldr.16 s4, [r1] +; DONT-FUSE-NEXT: vmov.f16 s0, #2.000000e+00 +; DONT-FUSE-NEXT: vfma.f16 s4, s2, s0 +; DONT-FUSE-NEXT: vstr.16 s4, [r0] ; DONT-FUSE-NEXT: bx lr %a = load half, ptr %aa, align 2 diff --git a/llvm/test/CodeGen/ARM/half.ll b/llvm/test/CodeGen/ARM/half.ll index 9f8c552cf8397..f12dffc857805 100644 --- a/llvm/test/CodeGen/ARM/half.ll +++ b/llvm/test/CodeGen/ARM/half.ll @@ -3,10 +3,10 @@ ; RUN: llc < %s -mtriple=thumbv8-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8 ; RUN: llc < %s -mtriple=armv8r-none-none-eabi -mattr=+neon,+fp-armv8 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8 ; RUN: llc < %s -mtriple=armv8r-none-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP -; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+fp-armv8 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8 -; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+fp-armv8,-fp64 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP -; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp,+fp64 | FileCheck %s --check-prefix=CHECK-V8 -; RUN: llc < %s -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-V8-SP +; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fp-armv8 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8 +; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fp-armv8,-fp64 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V8-SP +; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 | FileCheck %s --check-prefix=CHECK-V8 +; RUN: llc < %s -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp | FileCheck %s --check-prefix=CHECK-V8-SP define void @test_load_store(ptr %in, ptr %out) { ; CHECK-LABEL: test_load_store: diff --git a/llvm/test/CodeGen/ARM/interrupt-save-fp-attr.ll b/llvm/test/CodeGen/ARM/interrupt-save-fp-attr.ll index e96dfa4a38e12..a3d610059d00e 100644 --- a/llvm/test/CodeGen/ARM/interrupt-save-fp-attr.ll +++ b/llvm/test/CodeGen/ARM/interrupt-save-fp-attr.ll @@ -2,8 +2,8 @@ ; RUN: llc -mtriple=thumb-ti-none-eabihf -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A-THUMB %s ; RUN: llc -mtriple=thumb-ti-none-eabihf -mcpu=cortex-m4 -o - %s | FileCheck --check-prefix=CHECK-M %s ; RUN: llc -mtriple=thumbv7em-ti-none-eabihf -mcpu=cortex-m4 -o - %s | FileCheck --check-prefix=CHECK-M %s -; RUN: llc -mtriple=thumbv7r5-ti-none-eabihf -mcpu=cortex-r5 -o - %s | FileCheck --check-prefix=CHECK-R-THUMB %s -; RUN: llc -mtriple=armv7r5-ti-none-eabihf -mcpu=cortex-r5 -o - %s | FileCheck --check-prefix=CHECK-R %s +; RUN: llc -mtriple=thumbv7r-ti-none-eabihf -mcpu=cortex-r5 -o - %s | FileCheck --check-prefix=CHECK-R-THUMB %s +; RUN: llc -mtriple=armv7r-ti-none-eabihf -mcpu=cortex-r5 -o - %s | FileCheck --check-prefix=CHECK-R %s declare arm_aapcscc void @bar() diff --git a/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll b/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll index bce0bbabfdc29..8bdcc2e57899e 100644 --- a/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll +++ b/llvm/test/CodeGen/ARM/loop-align-cortex-m.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=thumbv7m-none-eabi %s -mcpu=cortex-m3 -o - | FileCheck %s ; RUN: llc -mtriple=thumbv7m-none-eabi %s -mcpu=cortex-m4 -o - | FileCheck %s -; RUN: llc -mtriple=thumbv8m-none-eabi %s -mcpu=cortex-m33 -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -mcpu=cortex-m33 -o - | FileCheck %s define void @test_loop_alignment(ptr %in, ptr %out) optsize { ; CHECK-LABEL: test_loop_alignment: diff --git a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll index 01cb3ba404816..a82cfcb76e159 100644 --- a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll +++ b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=armv7 -mattr=+neon %s -o - | FileCheck %s --check-prefix=ARMV7 ; RUN: llc -mtriple=armv7 -mattr=+fp-armv8 %s -o - | FileCheck %s --check-prefix=ARMV8 ; RUN: llc -mtriple=armv8.2a -mattr=+fp-armv8 %s -o - | FileCheck %s --check-prefix=ARMV8 -; RUN: llc -mtriple=armv8.1m-none-none-eabi -mattr=+mve.fp,+fp64 %s -o - | FileCheck %s --check-prefix=ARMV8M +; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 %s -o - | FileCheck %s --check-prefix=ARMV8M declare float @llvm.minnum.f32(float, float) declare float @llvm.maxnum.f32(float, float) @@ -999,11 +999,12 @@ define <2 x double> @fminnumv264_one_zero_intrinsic(<2 x double> %x) { ; ARMV8M-NEXT: vmov d1, r2, r3 ; ARMV8M-NEXT: vldr d0, .LCPI27_0 ; ARMV8M-NEXT: vcmp.f64 d1, #0 -; ARMV8M-NEXT: vmrs APSR_nzcv, fpscr ; ARMV8M-NEXT: vmov d2, r0, r1 +; ARMV8M-NEXT: vmrs APSR_nzcv, fpscr ; ARMV8M-NEXT: vmov.f64 d3, #-1.000000e+00 -; ARMV8M-NEXT: vcmp.f64 d3, d2 +; ARMV8M-NEXT: it lt ; ARMV8M-NEXT: vmovlt.f64 d0, d1 +; ARMV8M-NEXT: vcmp.f64 d3, d2 ; ARMV8M-NEXT: vmrs APSR_nzcv, fpscr ; ARMV8M-NEXT: vmov r2, r3, d0 ; ARMV8M-NEXT: vselgt.f64 d1, d2, d3 @@ -1312,7 +1313,7 @@ define void @pr65820(ptr %y, <4 x float> %splat) { ; ARMV8M-NEXT: vmov r1, s0 ; ARMV8M-NEXT: vmov.i32 q0, #0x0 ; ARMV8M-NEXT: vdup.32 q1, r1 -; ARMV8M-NEXT: vcmp.f32 gt, q1, zr +; ARMV8M-NEXT: vpt.f32 gt, q1, zr ; ARMV8M-NEXT: vdupt.32 q0, r1 ; ARMV8M-NEXT: vstrw.32 q0, [r0] ; ARMV8M-NEXT: bx lr diff --git a/llvm/test/CodeGen/ARM/useaa.ll b/llvm/test/CodeGen/ARM/useaa.ll index 9be0b88b35989..aca99ef83c0d4 100644 --- a/llvm/test/CodeGen/ARM/useaa.ll +++ b/llvm/test/CodeGen/ARM/useaa.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52plus | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA ; RUN: llc < %s -mtriple=armv7m-eabi -mcpu=cortex-m4 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA -; RUN: llc < %s -mtriple=armv8m-eabi -mcpu=cortex-m33 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA +; RUN: llc < %s -mtriple=thumbv8m.main-eabi -mcpu=cortex-m33 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA ; Check we use AA during codegen, so can interleave these loads/stores. diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll index 6d9dc46e1caa0..a7df97fc58b54 100644 --- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/lsr-profitable-chain.ll @@ -2,7 +2,7 @@ ; RUN: llc -O3 -tail-predication=enabled -mtriple=thumbv8.1m.main -mattr=+mve,+mve.fp %s -o - | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" -target triple = "thumbv8.1m-arm-none-eabi" +target triple = "thumbv8.1m.main-arm-none-eabi" ; Tests that LSR will not interfere with the VCTP intrinsic, ; and that this loop will correctly become tail-predicated. diff --git a/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll b/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll index a0f8374e074d9..50299d3abd305 100644 --- a/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll +++ b/llvm/test/CodeGen/Thumb2/aligned-nonfallthrough.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=thumbv8.1-m.main-none-eabi -mcpu=cortex-m55 -O3 < %s | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mcpu=cortex-m55 -O3 < %s | FileCheck %s define i32 @loop(ptr nocapture readonly %x) { ; CHECK-LABEL: loop: diff --git a/llvm/test/CodeGen/Thumb2/inlineasm-error-t-toofewregs-mve.ll b/llvm/test/CodeGen/Thumb2/inlineasm-error-t-toofewregs-mve.ll index 419ff71c07d14..c22cb39b38b4e 100644 --- a/llvm/test/CodeGen/Thumb2/inlineasm-error-t-toofewregs-mve.ll +++ b/llvm/test/CodeGen/Thumb2/inlineasm-error-t-toofewregs-mve.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mtriple=armv8.1-m-eabi -mattr=+mve %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve %s -o /dev/null 2>&1 | FileCheck %s ; CHECK: inline assembly requires more registers than available define arm_aapcs_vfpcc <4 x i32> @t-constraint-i32-vectors-too-few-regs(<4 x i32> %a, <4 x i32> %b) { diff --git a/llvm/test/CodeGen/Thumb2/inlineasm-mve.ll b/llvm/test/CodeGen/Thumb2/inlineasm-mve.ll index a8c0622b316ec..7fc9e4188248f 100644 --- a/llvm/test/CodeGen/Thumb2/inlineasm-mve.ll +++ b/llvm/test/CodeGen/Thumb2/inlineasm-mve.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=armv8.1-m-eabi -mattr=+mve %s -o - | FileCheck %s +; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve %s -o - | FileCheck %s define i32 @test1(i32 %tmp54) { %tmp56 = tail call i32 asm "uxtb16 $0,$1", "=r,r"( i32 %tmp54 ) @@ -22,10 +22,10 @@ define arm_aapcs_vfpcc <4 x i32> @mve-t-constraint-128bit(<4 x i32>, <4 x i32>) define i32 @even-GPR-constraint() { entry: ; CHECK-LABEL: even-GPR-constraint - ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #1 - ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #2 - ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #3 - ; CHECK: add [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #4 + ; CHECK: add.w [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #1 + ; CHECK: add.w [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #2 + ; CHECK: add.w [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #3 + ; CHECK: add.w [[REG:r1*[0, 2, 4, 6, 8]]], [[REG]], #4 %0 = tail call { i32, i32, i32, i32 } asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^Te,=^Te,=^Te,=^Te,0,1,2,3" (i32 0, i32 0, i32 0, i32 0) @@ -36,10 +36,10 @@ entry: define i32 @odd-GPR-constraint() { entry: ; CHECK-LABEL: odd-GPR-constraint - ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #1 - ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #2 - ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #3 - ; CHECK: add [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #4 + ; CHECK: add.w [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #1 + ; CHECK: add.w [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #2 + ; CHECK: add.w [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #3 + ; CHECK: add.w [[REG:r1*[1, 3, 5, 7, 9]]], [[REG]], #4 %0 = tail call { i32, i32, i32, i32 } asm "add $0, #1\0Aadd $1, #2\0Aadd $2, #3\0Aadd $3, #4\0A", "=^To,=^To,=^To,=^To,0,1,2,3" (i32 0, i32 0, i32 0, i32 0) diff --git a/llvm/test/CodeGen/Thumb2/unreachable-large-offset-gep.ll b/llvm/test/CodeGen/Thumb2/unreachable-large-offset-gep.ll index 00710c3ed3681..8231a6b50437c 100644 --- a/llvm/test/CodeGen/Thumb2/unreachable-large-offset-gep.ll +++ b/llvm/test/CodeGen/Thumb2/unreachable-large-offset-gep.ll @@ -3,7 +3,7 @@ ; CHECK: .LBB0_1: ; CHECK: b .LBB0_1 -target triple = "thumbv8m-unknown-linux-android" +target triple = "thumbv8m.main-unknown-linux-android" define void @d(ptr %c) { entry: diff --git a/llvm/test/MC/ARM/ras-extension.s b/llvm/test/MC/ARM/ras-extension.s index b206cff2d33e5..e803a1921cedd 100644 --- a/llvm/test/MC/ARM/ras-extension.s +++ b/llvm/test/MC/ARM/ras-extension.s @@ -1,7 +1,7 @@ @ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+ras -show-encoding %s | FileCheck %s --check-prefix=ARM @ RUN: llvm-mc -triple thumbv8a-none-eabi -mattr=+ras -show-encoding %s | FileCheck %s --check-prefix=THUMB @ RUN: llvm-mc -triple thumbv8.1m.main-none-eabi -show-encoding %s | FileCheck %s --check-prefix=THUMB -@ RUN: not llvm-mc -triple thumbv8m-none-eabi -show-encoding %s 2>&1 | FileCheck %s --check-prefix=FAIL +@ RUN: not llvm-mc -triple thumbv8m.main-none-eabi -show-encoding %s 2>&1 | FileCheck %s --check-prefix=FAIL esb @ ARM: esb @ encoding: [0x10,0xf0,0x20,0xe3] diff --git a/llvm/test/MC/Disassembler/ARM/ras-extension-thumb.txt b/llvm/test/MC/Disassembler/ARM/ras-extension-thumb.txt index da0d01f996e28..5c5a02f574927 100644 --- a/llvm/test/MC/Disassembler/ARM/ras-extension-thumb.txt +++ b/llvm/test/MC/Disassembler/ARM/ras-extension-thumb.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc < %s -triple thumbv8a-none-eabi -mattr=+ras -disassemble | FileCheck %s --check-prefix=RAS # RUN: llvm-mc < %s -triple thumbv8a-none-eabi -mattr=-ras -disassemble | FileCheck %s --check-prefix=NO-RAS # RUN: llvm-mc < %s -triple=thumbv8.1m.main-none-eabi -disassemble | FileCheck %s --check-prefix=RAS -# RUN: not llvm-mc < %s -triple=thumbv8m-none-eabi -disassemble 2>&1 | FileCheck %s --check-prefix=FAIL +# RUN: not llvm-mc < %s -triple=thumbv8m.base-none-eabi -disassemble 2>&1 | FileCheck %s --check-prefix=FAIL [0xaf,0xf3,0x10,0x80] # RAS: esb diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/memory-intrinsics.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/memory-intrinsics.ll index 9bec9b53ed0cd..b4bb032a7ee3a 100644 --- a/llvm/test/Transforms/CodeGenPrepare/ARM/memory-intrinsics.ll +++ b/llvm/test/Transforms/CodeGenPrepare/ARM/memory-intrinsics.ll @@ -1,4 +1,4 @@ -; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -mtriple=arm7-unknown-unknown -S < %s | FileCheck %s +; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -mtriple=armv7-unknown-unknown -S < %s | FileCheck %s declare void @llvm.memcpy.p0.p0.i32(ptr, ptr, i32, i1) nounwind declare void @llvm.memmove.p0.p0.i32(ptr, ptr, i32, i1) nounwind diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltpoison.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltpoison.ll index 2c29f2343290e..96b6ce5a8c318 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltpoison.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltpoison.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -mtriple=thumbv8.1m.main -mattr=+mve %s -S -loop-reduce -o - | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" -target triple = "thumbv8.1m-arm-none-eabi" +target triple = "thumbv8.1m.main-arm-none-eabi" define float @vctp8(ptr %0, i32 %1) { ; CHECK-LABEL: @vctp8( diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains.ll index 064b98e51c3e9..80dcad1263d22 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -mtriple=thumbv8.1m.main -mattr=+mve %s -S -loop-reduce -o - | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" -target triple = "thumbv8.1m-arm-none-eabi" +target triple = "thumbv8.1m.main-arm-none-eabi" define float @vctp8(ptr %0, i32 %1) { ; CHECK-LABEL: @vctp8( diff --git a/llvm/test/tools/llvm-mca/ARM/m4-int.s b/llvm/test/tools/llvm-mca/ARM/m4-int.s index d2c7658048185..452abcd53f95c 100644 --- a/llvm/test/tools/llvm-mca/ARM/m4-int.s +++ b/llvm/test/tools/llvm-mca/ARM/m4-int.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv7-m-none-none-eabi -mcpu=cortex-m4 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv7em-none-none-eabi -mcpu=cortex-m4 -instruction-tables < %s | FileCheck %s adc r0, r1, #0 adcs r0, r1, #0 diff --git a/llvm/test/tools/llvm-mca/ARM/m55-fp.s b/llvm/test/tools/llvm-mca/ARM/m55-fp.s index 1668f58c7937f..5f40ea56186a8 100644 --- a/llvm/test/tools/llvm-mca/ARM/m55-fp.s +++ b/llvm/test/tools/llvm-mca/ARM/m55-fp.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m55 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m55 -instruction-tables < %s | FileCheck %s vabs.f16 s0, s2 vabs.f32 s0, s2 diff --git a/llvm/test/tools/llvm-mca/ARM/m55-int.s b/llvm/test/tools/llvm-mca/ARM/m55-int.s index 4481b62b1969a..7f152f0691cc3 100644 --- a/llvm/test/tools/llvm-mca/ARM/m55-int.s +++ b/llvm/test/tools/llvm-mca/ARM/m55-int.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m55 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m55 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s adc r0, r1, #0 adcs r0, r1, #0 diff --git a/llvm/test/tools/llvm-mca/ARM/m55-mve-fp.s b/llvm/test/tools/llvm-mca/ARM/m55-mve-fp.s index bcbd3c97f2162..73ccf7b9a54cf 100644 --- a/llvm/test/tools/llvm-mca/ARM/m55-mve-fp.s +++ b/llvm/test/tools/llvm-mca/ARM/m55-mve-fp.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m55 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m55 -instruction-tables < %s | FileCheck %s vabd.f16 q0, q2, q1 vabd.f32 q0, q2, q1 diff --git a/llvm/test/tools/llvm-mca/ARM/m55-mve-int.s b/llvm/test/tools/llvm-mca/ARM/m55-mve-int.s index c2b827fe81534..7b3483706f5ca 100644 --- a/llvm/test/tools/llvm-mca/ARM/m55-mve-int.s +++ b/llvm/test/tools/llvm-mca/ARM/m55-mve-int.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m55 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m55 -instruction-tables < %s | FileCheck %s vabav.s8 r0, q2, q1 vabav.u8 r0, q2, q1 diff --git a/llvm/test/tools/llvm-mca/ARM/m55-mve-ldst.s b/llvm/test/tools/llvm-mca/ARM/m55-mve-ldst.s index 8e06105933aed..b39a72daa3605 100644 --- a/llvm/test/tools/llvm-mca/ARM/m55-mve-ldst.s +++ b/llvm/test/tools/llvm-mca/ARM/m55-mve-ldst.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m55 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m55 -instruction-tables < %s | FileCheck %s vldrb.8 q1, [r0, 0] vldrb.8 q1, [r0, 0]! diff --git a/llvm/test/tools/llvm-mca/ARM/m55-mve-pred.s b/llvm/test/tools/llvm-mca/ARM/m55-mve-pred.s index 9add5ce1c39fd..ecf243cdf3ec9 100644 --- a/llvm/test/tools/llvm-mca/ARM/m55-mve-pred.s +++ b/llvm/test/tools/llvm-mca/ARM/m55-mve-pred.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m55 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m55 -instruction-tables < %s | FileCheck %s vcmp.f16 eq, q2, q1 vcmp.f32 eq, q2, q1 diff --git a/llvm/test/tools/llvm-mca/ARM/m55-storefwd.s b/llvm/test/tools/llvm-mca/ARM/m55-storefwd.s index 3bdaf57e00483..4a50092e3b42c 100644 --- a/llvm/test/tools/llvm-mca/ARM/m55-storefwd.s +++ b/llvm/test/tools/llvm-mca/ARM/m55-storefwd.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m55 -timeline < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m55 -timeline < %s | FileCheck %s # Most MVE operations are either latency=1 or can forward into stores vadd.i8 q0, q2, q1 diff --git a/llvm/test/tools/llvm-mca/ARM/m7-fp.s b/llvm/test/tools/llvm-mca/ARM/m7-fp.s index dba7ff92f30cb..20ecfc5cdcbdf 100644 --- a/llvm/test/tools/llvm-mca/ARM/m7-fp.s +++ b/llvm/test/tools/llvm-mca/ARM/m7-fp.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv7-m.main-none-none-eabi -mcpu=cortex-m7 -mattr=+fp64 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv7em-none-none-eabi -mcpu=cortex-m7 -mattr=+fp64 -instruction-tables < %s | FileCheck %s vabs.f32 s0, s2 vabs.f64 d0, d2 diff --git a/llvm/test/tools/llvm-mca/ARM/m7-int.s b/llvm/test/tools/llvm-mca/ARM/m7-int.s index 78cc679239f00..aa8f7f860b335 100644 --- a/llvm/test/tools/llvm-mca/ARM/m7-int.s +++ b/llvm/test/tools/llvm-mca/ARM/m7-int.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv7-m.main-none-none-eabi -mcpu=cortex-m7 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv7em-none-none-eabi -mcpu=cortex-m7 -instruction-tables < %s | FileCheck %s adc r0, r1, #0 adcs r0, r1, #0 diff --git a/llvm/test/tools/llvm-mca/ARM/m85-fp.s b/llvm/test/tools/llvm-mca/ARM/m85-fp.s index 0fc1b394de2dc..79a3d67e02d0c 100644 --- a/llvm/test/tools/llvm-mca/ARM/m85-fp.s +++ b/llvm/test/tools/llvm-mca/ARM/m85-fp.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+fp64,+fp16 -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+fp64,+fp16 -instruction-tables < %s | FileCheck %s vabs.f16 s0, s2 vabs.f32 s0, s2 diff --git a/llvm/test/tools/llvm-mca/ARM/m85-int.s b/llvm/test/tools/llvm-mca/ARM/m85-int.s index cb1f991371ea1..3b16ba706d560 100644 --- a/llvm/test/tools/llvm-mca/ARM/m85-int.s +++ b/llvm/test/tools/llvm-mca/ARM/m85-int.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s adc r0, r1, #0 adcs r0, r1, #0 diff --git a/llvm/test/tools/llvm-mca/ARM/m85-mve-fp.s b/llvm/test/tools/llvm-mca/ARM/m85-mve-fp.s index 57a885951056c..768709805763d 100644 --- a/llvm/test/tools/llvm-mca/ARM/m85-mve-fp.s +++ b/llvm/test/tools/llvm-mca/ARM/m85-mve-fp.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s vabd.f16 q0, q2, q1 vabd.f32 q0, q2, q1 diff --git a/llvm/test/tools/llvm-mca/ARM/m85-mve-int.s b/llvm/test/tools/llvm-mca/ARM/m85-mve-int.s index a98dec28f79bf..8cfd835c4028a 100644 --- a/llvm/test/tools/llvm-mca/ARM/m85-mve-int.s +++ b/llvm/test/tools/llvm-mca/ARM/m85-mve-int.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s vabav.s8 r0, q2, q1 vabav.u8 r0, q2, q1 diff --git a/llvm/test/tools/llvm-mca/ARM/m85-mve-pred.s b/llvm/test/tools/llvm-mca/ARM/m85-mve-pred.s index 5e787a410e32a..8e931cdcb45f5 100644 --- a/llvm/test/tools/llvm-mca/ARM/m85-mve-pred.s +++ b/llvm/test/tools/llvm-mca/ARM/m85-mve-pred.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=thumbv8.1-m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s +# RUN: llvm-mca -mtriple=thumbv8.1m.main-none-none-eabi -mcpu=cortex-m85 -mattr=+mve.fp -instruction-tables < %s | FileCheck %s vcmp.f16 eq, q2, q1 vcmp.f32 eq, q2, q1 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
