================
@@ -1527,6 +1557,13 @@ void
SITargetLowering::getTgtMemIntrinsic(SmallVectorImpl<IntrinsicInfo> &Infos,
// XXX - Should this be volatile without known ordering?
Info.flags |= MachineMemOperand::MOVolatile;
Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType());
+ if (std::optional<SyncScope::ID> SSID =
+ parseBufferAtomicScopeArg(CI)) {
+ // Pretend to be atomic so expandAtomicCmpxchgOrRmw sets cache
+ // bypass bits.
+ Info.order = AtomicOrdering::Monotonic;
----------------
krzysz00 wrote:
... yeah, if you're doing this, I want the atomic strength to be in there.
Alternatively, we could avoid all this by calling the "set cache bits for this
scope" over in LowerBufferFatPointers, no?
https://github.com/llvm/llvm-project/pull/213585
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