https://github.com/banach-space created https://github.com/llvm/llvm-project/pull/217017
This PR adds lowering for intrinsic from the following groups: * https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions It continues the work started in #190961, #193273, #199990, #209252, #211609 and #216757. This PR implements the conversions for the following "truncating to nearest" intrinsics: * vcvtnd_s32_f64 * vcvtnd_s64_f64 * vcvtnd_u32_f64 * vcvtnd_u64_f64 The corresponding tests are moved from: * clang/test/CodeGen/AArch64/ to: * clang/test/CodeGen/AArch64/neon/ The lowering follows the existing implementation in CodeGen/TargetBuiltins/ARM.cpp. From b9f1bd3c26d96e52eaf9413db6636c200fd3e188 Mon Sep 17 00:00:00 2001 From: Andrzej Warzynski <[email protected]> Date: Tue, 18 Aug 2026 12:51:37 +0000 Subject: [PATCH] [clang][CIR][AArch64] Add lowering for conversion intrinsics () This PR adds lowering for intrinsic from the following groups: * https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions It continues the work started in #190961, #193273, #199990, #209252, #211609 and #216757. This PR implements the conversions for the following "truncating to nearest" intrinsics: * vcvtnd_s32_f64 * vcvtnd_s64_f64 * vcvtnd_u32_f64 * vcvtnd_u64_f64 The corresponding tests are moved from: * clang/test/CodeGen/AArch64/ to: * clang/test/CodeGen/AArch64/neon/ The lowering follows the existing implementation in CodeGen/TargetBuiltins/ARM.cpp. --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 4 ++ .../CodeGen/AArch64/neon-fcvt-intrinsics.c | 40 ------------------- clang/test/CodeGen/AArch64/neon/intrinsics.c | 40 +++++++++++++++++++ 3 files changed, 44 insertions(+), 40 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index bb20e8f3ed73d..469dd4518f201 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -455,6 +455,10 @@ emitCommonNeonSISDBuiltinExpr(CIRGenFunction &cgf, case NEON::BI__builtin_neon_vcvtns_s64_f32: case NEON::BI__builtin_neon_vcvtns_u32_f32: case NEON::BI__builtin_neon_vcvtns_u64_f32: + case NEON::BI__builtin_neon_vcvtnd_s32_f64: + case NEON::BI__builtin_neon_vcvtnd_s64_f64: + case NEON::BI__builtin_neon_vcvtnd_u32_f64: + case NEON::BI__builtin_neon_vcvtnd_u64_f64: case NEON::BI__builtin_neon_vaddlv_s32: case NEON::BI__builtin_neon_vaddlv_u32: case NEON::BI__builtin_neon_vaddlvq_s32: diff --git a/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c b/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c index d1c76e0250549..73c9f1d6e859f 100644 --- a/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-fcvt-intrinsics.c @@ -176,46 +176,6 @@ uint32_t test_vcvtmd_u32_f64(float64_t a) { return (uint32_t)vcvtmd_u32_f64(a); } -// CHECK-LABEL: define {{[^@]+}}@test_vcvtnd_s64_f64 -// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VCVTND_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double [[A]]) -// CHECK-NEXT: ret i64 [[VCVTND_S64_F64_I]] -// -int64_t test_vcvtnd_s64_f64(float64_t a) { - return (int64_t)vcvtnd_s64_f64(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vcvtnd_s32_f64 -// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VCVTND_S32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtns.i32.f64(double [[A]]) -// CHECK-NEXT: ret i32 [[VCVTND_S32_F64_I]] -// -int32_t test_vcvtnd_s32_f64(float64_t a) { - return (int32_t)vcvtnd_s32_f64(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vcvtnd_u64_f64 -// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VCVTND_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double [[A]]) -// CHECK-NEXT: ret i64 [[VCVTND_U64_F64_I]] -// -uint64_t test_vcvtnd_u64_f64(float64_t a) { - return (uint64_t)vcvtnd_u64_f64(a); -} - -// CHECK-LABEL: define {{[^@]+}}@test_vcvtnd_u32_f64 -// CHECK-SAME: (double noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: entry: -// CHECK-NEXT: [[VCVTND_U32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double [[A]]) -// CHECK-NEXT: ret i32 [[VCVTND_U32_F64_I]] -// -uint32_t test_vcvtnd_u32_f64(float64_t a) { - return (uint32_t)vcvtnd_u32_f64(a); -} - // CHECK-LABEL: define {{[^@]+}}@test_vcvtps_s32_f32 // CHECK-SAME: (float noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 31eb0205389c6..ce9b132d52adb 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -4842,6 +4842,46 @@ uint64x2_t test_vcvtnq_u64_f64(float64x2_t a) { return vcvtnq_u64_f64(a); } +// LLVM-LABEL: @test_vcvtnd_s64_f64 +int64_t test_vcvtnd_s64_f64(float64_t a) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtns" + +// LLVM-SAME: double {{.*}} [[A:%.*]]) +// LLVM: [[VCVTND_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double [[A]]) +// LLVM: ret i64 [[VCVTND_S64_F64_I]] + return (int64_t)vcvtnd_s64_f64(a); +} + +// LLVM-LABEL: @test_vcvtnd_s32_f64 +int32_t test_vcvtnd_s32_f64(float64_t a) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtns" + +// LLVM-SAME: double {{.*}} [[A:%.*]]) +// LLVM: [[VCVTND_S32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtns.i32.f64(double [[A]]) +// LLVM: ret i32 [[VCVTND_S32_F64_I]] + return (int32_t)vcvtnd_s32_f64(a); +} + +// LLVM-LABEL: define {{[^@]+}}@test_vcvtnd_u64_f64 +uint64_t test_vcvtnd_u64_f64(float64_t a) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtnu" + + return (uint64_t)vcvtnd_u64_f64(a); +// LLVM-SAME: double {{.*}} [[A:%.*]]) +// LLVM: [[VCVTND_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double [[A]]) +// LLVM: ret i64 [[VCVTND_U64_F64_I]] +} + +// LLVM-LABEL: @test_vcvtnd_u32_f64 +uint32_t test_vcvtnd_u32_f64(float64_t a) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.fcvtnu" + +// LLVM-SAME: double {{.*}} [[A:%.*]]) +// LLVM: [[VCVTND_U32_F64_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double [[A]]) +// LLVM: ret i32 [[VCVTND_U32_F64_I]] + return (uint32_t)vcvtnd_u32_f64(a); +} + //===------------------------------------------------------===// // 2.1.3.2.3 Vector shift right and accumulate // https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-accumulate _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
